r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t num_rts,
bool layered_clear)
{
+ struct ir3_const_state dummy_const_state = {};
struct ir3_shader dummy_shader = {};
struct ir3_shader_variant vs = {
.regid = regid(1, 0),
},
.shader = &dummy_shader,
+ .const_state = &dummy_const_state,
};
if (layered_clear) {
vs = (struct ir3_shader_variant) {
.instrlen = 1,
.info.max_reg = 0,
.shader = &dummy_shader,
+ .const_state = &dummy_const_state,
};
}
.cmd = 4,
},
.shader = &dummy_shader,
+ .const_state = &dummy_const_state,
};
struct ir3_shader_variant gs_shader = {
.regid = regid(1, 0),
},
.shader = &dummy_shader,
+ .const_state = &dummy_const_state,
}, *gs = layered_clear ? &gs_shader : NULL;
#define GS_OFFSET (32 * sizeof(instr_t))
/* shaders */
- struct ts_cs_memory shaders = { };
+ struct tu_cs_memory shaders = { };
VkResult result = tu_cs_alloc(&cmd->sub_cs, 2 + layered_clear,
16 * sizeof(instr_t), &shaders);
assert(result == VK_SUCCESS);
tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0());
tu_cs_emit_regs(cs, A6XX_VFD_CONTROL_0());
- tu6_emit_vpc(cs, &vs, gs, &fs, NULL);
+ tu6_emit_vpc(cs, &vs, NULL, NULL, gs, &fs);
/* REPL_MODE for varying with RECTLIST (2 vertices only) */
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_INTERP_MODE(0, 0));
uint32_t offset_ubwc,
VkFilter filter)
{
- struct ts_cs_memory texture = { };
+ struct tu_cs_memory texture = { };
VkResult result = tu_cs_alloc(&cmd->sub_cs,
2, /* allocate space for a sampler too */
A6XX_TEX_CONST_DWORDS, &texture);
tu_bo_list_add(&cmd->bo_list, buffer->bo, MSM_SUBMIT_BO_WRITE);
- struct ts_cs_memory tmp;
+ struct tu_cs_memory tmp;
VkResult result = tu_cs_alloc(&cmd->sub_cs, DIV_ROUND_UP(dataSize, 64), 64, &tmp);
if (result != VK_SUCCESS) {
cmd->record_result = result;