#include "vk_format.h"
#include "tu_cs.h"
-#include "tu_blit.h"
#define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
return VK_SUCCESS;
}
-static bool
-is_linear_mipmapped(const struct tu_image_view *iview)
-{
- return iview->image->layout.tile_mode == TILE6_LINEAR &&
- iview->base_mip != iview->image->level_count - 1;
-}
-
-static bool
-force_sysmem(const struct tu_cmd_buffer *cmd,
- const struct VkRect2D *render_area)
-{
- const struct tu_framebuffer *fb = cmd->state.framebuffer;
- const struct tu_physical_device *device = cmd->device->physical_device;
- bool has_linear_mipmapped_store = false;
- const struct tu_render_pass *pass = cmd->state.pass;
-
- /* Layered rendering requires sysmem. */
- if (fb->layers > 1)
- return true;
-
- /* Iterate over all the places we call tu6_emit_store_attachment() */
- for (unsigned i = 0; i < pass->subpass_count; i++) {
- const struct tu_subpass *subpass = &pass->subpasses[i];
- if (subpass->resolve_attachments) {
- for (unsigned i = 0; i < subpass->color_count; i++) {
- uint32_t a = subpass->resolve_attachments[i].attachment;
- if (a != VK_ATTACHMENT_UNUSED &&
- cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
- const struct tu_image_view *iview = fb->attachments[a].attachment;
- if (is_linear_mipmapped(iview)) {
- has_linear_mipmapped_store = true;
- break;
- }
- }
- }
- }
- }
-
- for (unsigned i = 0; i < pass->attachment_count; i++) {
- if (pass->attachments[i].gmem_offset >= 0 &&
- cmd->state.pass->attachments[i].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
- const struct tu_image_view *iview = fb->attachments[i].attachment;
- if (is_linear_mipmapped(iview)) {
- has_linear_mipmapped_store = true;
- break;
- }
- }
- }
-
- /* Linear textures cannot have any padding between mipmap levels and their
- * height isn't padded, while at the same time the GMEM->MEM resolve does
- * not have per-pixel granularity, so if the image height isn't aligned to
- * the resolve granularity and the render area is tall enough, we may wind
- * up writing past the bottom of the image into the next miplevel or even
- * past the end of the image. For the last miplevel, the layout code should
- * insert enough padding so that the overdraw writes to the padding. To
- * work around this, we force-enable sysmem rendering.
- */
- const uint32_t y2 = render_area->offset.y + render_area->extent.height;
- const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
-
- return has_linear_mipmapped_store && aligned_y2 > fb->height;
-}
-
static void
tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
const struct tu_device *dev,
- uint32_t pixels)
+ const struct tu_render_pass *pass)
{
- const uint32_t tile_align_w = dev->physical_device->tile_align_w;
- const uint32_t tile_align_h = dev->physical_device->tile_align_h;
- const uint32_t max_tile_width = 1024; /* A6xx */
+ const uint32_t tile_align_w = pass->tile_align_w;
+ const uint32_t max_tile_width = 1024;
/* note: don't offset the tiling config by render_area.offset,
* because binning pass can't deal with it
.height = 1,
};
tiling->tile0.extent = (VkExtent2D) {
- .width = align(ra_width, tile_align_w),
- .height = align(ra_height, tile_align_h),
+ .width = util_align_npot(ra_width, tile_align_w),
+ .height = align(ra_height, TILE_ALIGN_H),
};
if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
/* start with 2x2 tiles */
tiling->tile_count.width = 2;
tiling->tile_count.height = 2;
- tiling->tile0.extent.width = align(DIV_ROUND_UP(ra_width, 2), tile_align_w);
- tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), tile_align_h);
+ tiling->tile0.extent.width = util_align_npot(DIV_ROUND_UP(ra_width, 2), tile_align_w);
+ tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), TILE_ALIGN_H);
}
/* do not exceed max tile width */
while (tiling->tile0.extent.width > max_tile_width) {
tiling->tile_count.width++;
tiling->tile0.extent.width =
- align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
+ util_align_npot(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
}
/* will force to sysmem, don't bother trying to have a valid tile config
* TODO: just skip all GMEM stuff when sysmem is forced?
*/
- if (!pixels)
+ if (!pass->gmem_pixels)
return;
/* do not exceed gmem size */
- while (tiling->tile0.extent.width * tiling->tile0.extent.height > pixels) {
+ while (tiling->tile0.extent.width * tiling->tile0.extent.height > pass->gmem_pixels) {
if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
tiling->tile_count.width++;
tiling->tile0.extent.width =
- align(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
+ util_align_npot(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
} else {
/* if this assert fails then layout is impossible.. */
- assert(tiling->tile0.extent.height > tile_align_h);
+ assert(tiling->tile0.extent.height > TILE_ALIGN_H);
tiling->tile_count.height++;
tiling->tile0.extent.height =
- align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), tile_align_h);
+ align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), TILE_ALIGN_H);
}
}
}
}
}
-unsigned
+void
tu6_emit_event_write(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
- enum vgt_event_type event,
- bool need_seqno)
-{
- unsigned seqno = 0;
+ enum vgt_event_type event)
+{
+ bool need_seqno = false;
+ switch (event) {
+ case CACHE_FLUSH_TS:
+ case WT_DONE_TS:
+ case RB_DONE_TS:
+ case PC_CCU_FLUSH_DEPTH_TS:
+ case PC_CCU_FLUSH_COLOR_TS:
+ case PC_CCU_RESOLVE_TS:
+ need_seqno = true;
+ break;
+ default:
+ break;
+ }
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
if (need_seqno) {
tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
- seqno = ++cmd->scratch_seqno;
- tu_cs_emit(cs, seqno);
+ tu_cs_emit(cs, 0);
}
+}
- return seqno;
+static void
+tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer,
+ struct tu_cs *cs,
+ enum tu_cmd_flush_bits flushes)
+{
+ /* Experiments show that invalidating CCU while it still has data in it
+ * doesn't work, so make sure to always flush before invalidating in case
+ * any data remains that hasn't yet been made available through a barrier.
+ * However it does seem to work for UCHE.
+ */
+ if (flushes & (TU_CMD_FLAG_CCU_FLUSH_COLOR |
+ TU_CMD_FLAG_CCU_INVALIDATE_COLOR))
+ tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_COLOR_TS);
+ if (flushes & (TU_CMD_FLAG_CCU_FLUSH_DEPTH |
+ TU_CMD_FLAG_CCU_INVALIDATE_DEPTH))
+ tu6_emit_event_write(cmd_buffer, cs, PC_CCU_FLUSH_DEPTH_TS);
+ if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_COLOR)
+ tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_COLOR);
+ if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_DEPTH)
+ tu6_emit_event_write(cmd_buffer, cs, PC_CCU_INVALIDATE_DEPTH);
+ if (flushes & TU_CMD_FLAG_CACHE_FLUSH)
+ tu6_emit_event_write(cmd_buffer, cs, CACHE_FLUSH_TS);
+ if (flushes & TU_CMD_FLAG_CACHE_INVALIDATE)
+ tu6_emit_event_write(cmd_buffer, cs, CACHE_INVALIDATE);
+ if (flushes & TU_CMD_FLAG_WFI)
+ tu_cs_emit_wfi(cs);
}
+/* "Normal" cache flushes, that don't require any special handling */
+
static void
-tu6_emit_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
+tu_emit_cache_flush(struct tu_cmd_buffer *cmd_buffer,
+ struct tu_cs *cs)
{
- tu6_emit_event_write(cmd, cs, 0x31, false);
+ tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits);
+ cmd_buffer->state.cache.flush_bits = 0;
}
-static void
-tu6_emit_lrz_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
+/* Renderpass cache flushes */
+
+void
+tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer,
+ struct tu_cs *cs)
{
- tu6_emit_event_write(cmd, cs, LRZ_FLUSH, false);
+ tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits);
+ cmd_buffer->state.renderpass_cache.flush_bits = 0;
}
-static void
-tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
+/* Cache flushes for things that use the color/depth read/write path (i.e.
+ * blits and draws). This deals with changing CCU state as well as the usual
+ * cache flushing.
+ */
+
+void
+tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
+ struct tu_cs *cs,
+ enum tu_cmd_ccu_state ccu_state)
{
- if (cmd->wait_for_idle) {
- tu_cs_emit_wfi(cs);
- cmd->wait_for_idle = false;
+ enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits;
+
+ assert(ccu_state != TU_CMD_CCU_UNKNOWN);
+
+ /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
+ * the CCU may also contain data that we haven't flushed out yet, so we
+ * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
+ * emit a WFI as it isn't pipelined.
+ */
+ if (ccu_state != cmd_buffer->state.ccu_state) {
+ if (cmd_buffer->state.ccu_state != TU_CMD_CCU_GMEM) {
+ flushes |=
+ TU_CMD_FLAG_CCU_FLUSH_COLOR |
+ TU_CMD_FLAG_CCU_FLUSH_DEPTH;
+ cmd_buffer->state.cache.pending_flush_bits &= ~(
+ TU_CMD_FLAG_CCU_FLUSH_COLOR |
+ TU_CMD_FLAG_CCU_FLUSH_DEPTH);
+ }
+ flushes |=
+ TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
+ TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
+ TU_CMD_FLAG_WFI;
+ cmd_buffer->state.cache.pending_flush_bits &= ~(
+ TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
+ TU_CMD_FLAG_CCU_INVALIDATE_DEPTH);
}
-}
-#define tu_image_view_ubwc_pitches(iview) \
- .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip), \
- .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
+ tu6_emit_flushes(cmd_buffer, cs, flushes);
+ cmd_buffer->state.cache.flush_bits = 0;
+
+ if (ccu_state != cmd_buffer->state.ccu_state) {
+ struct tu_physical_device *phys_dev = cmd_buffer->device->physical_device;
+ tu_cs_emit_regs(cs,
+ A6XX_RB_CCU_CNTL(.offset =
+ ccu_state == TU_CMD_CCU_GMEM ?
+ phys_dev->ccu_offset_gmem :
+ phys_dev->ccu_offset_bypass,
+ .gmem = ccu_state == TU_CMD_CCU_GMEM));
+ cmd_buffer->state.ccu_state = ccu_state;
+ }
+}
static void
tu6_emit_zs(struct tu_cmd_buffer *cmd,
}
const struct tu_image_view *iview = fb->attachments[a].attachment;
- enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
+ const struct tu_render_pass_attachment *attachment =
+ &cmd->state.pass->attachments[a];
+ enum a6xx_depth_format fmt = tu6_pipe2depth(attachment->format);
- tu_cs_emit_regs(cs,
- A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
- A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview->image, iview->base_mip)),
- A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview->image->layout.layer_size),
- A6XX_RB_DEPTH_BUFFER_BASE(tu_image_view_base_ref(iview)),
- A6XX_RB_DEPTH_BUFFER_BASE_GMEM(cmd->state.pass->attachments[a].gmem_offset));
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
+ tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt).value);
+ tu_cs_image_ref(cs, iview, 0);
+ tu_cs_emit(cs, attachment->gmem_offset);
tu_cs_emit_regs(cs,
A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
- tu_cs_emit_regs(cs,
- A6XX_RB_DEPTH_FLAG_BUFFER_BASE(tu_image_view_ubwc_base_ref(iview)),
- A6XX_RB_DEPTH_FLAG_BUFFER_PITCH(tu_image_view_ubwc_pitches(iview)));
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
+ tu_cs_image_flag_ref(cs, iview, 0);
tu_cs_emit_regs(cs,
A6XX_GRAS_LRZ_BUFFER_BASE(0),
A6XX_GRAS_LRZ_BUFFER_PITCH(0),
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
- tu_cs_emit_regs(cs,
- A6XX_RB_STENCIL_INFO(0));
-
- /* enable zs? */
+ if (attachment->format == VK_FORMAT_S8_UINT) {
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
+ tu_cs_emit(cs, A6XX_RB_STENCIL_INFO(.separate_stencil = true).value);
+ tu_cs_image_ref(cs, iview, 0);
+ tu_cs_emit(cs, attachment->gmem_offset);
+ } else {
+ tu_cs_emit_regs(cs,
+ A6XX_RB_STENCIL_INFO(0));
+ }
}
static void
struct tu_cs *cs)
{
const struct tu_framebuffer *fb = cmd->state.framebuffer;
- unsigned char mrt_comp[MAX_RTS] = { 0 };
- unsigned srgb_cntl = 0;
for (uint32_t i = 0; i < subpass->color_count; ++i) {
uint32_t a = subpass->color_attachments[i].attachment;
continue;
const struct tu_image_view *iview = fb->attachments[a].attachment;
- const enum a6xx_tile_mode tile_mode =
- tu6_get_image_tile_mode(iview->image, iview->base_mip);
- mrt_comp[i] = 0xf;
-
- if (vk_format_is_srgb(iview->vk_format))
- srgb_cntl |= (1 << i);
-
- const struct tu_native_format format =
- tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
-
- tu_cs_emit_regs(cs,
- A6XX_RB_MRT_BUF_INFO(i,
- .color_tile_mode = tile_mode,
- .color_format = format.fmt,
- .color_swap = format.swap),
- A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
- A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
- A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
- A6XX_RB_MRT_BASE_GMEM(i, cmd->state.pass->attachments[a].gmem_offset));
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
+ tu_cs_emit(cs, iview->RB_MRT_BUF_INFO);
+ tu_cs_image_ref(cs, iview, 0);
+ tu_cs_emit(cs, cmd->state.pass->attachments[a].gmem_offset);
tu_cs_emit_regs(cs,
- A6XX_SP_FS_MRT_REG(i,
- .color_format = format.fmt,
- .color_sint = vk_format_is_sint(iview->vk_format),
- .color_uint = vk_format_is_uint(iview->vk_format)));
+ A6XX_SP_FS_MRT_REG(i, .dword = iview->SP_FS_MRT_REG));
- tu_cs_emit_regs(cs,
- A6XX_RB_MRT_FLAG_BUFFER_ADDR(i, tu_image_view_ubwc_base_ref(iview)),
- A6XX_RB_MRT_FLAG_BUFFER_PITCH(i, tu_image_view_ubwc_pitches(iview)));
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i), 3);
+ tu_cs_image_flag_ref(cs, iview, 0);
}
tu_cs_emit_regs(cs,
- A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
-
- tu_cs_emit_regs(cs,
- A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
-
+ A6XX_RB_SRGB_CNTL(.dword = subpass->srgb_cntl));
tu_cs_emit_regs(cs,
- A6XX_RB_RENDER_COMPONENTS(
- .rt0 = mrt_comp[0],
- .rt1 = mrt_comp[1],
- .rt2 = mrt_comp[2],
- .rt3 = mrt_comp[3],
- .rt4 = mrt_comp[4],
- .rt5 = mrt_comp[5],
- .rt6 = mrt_comp[6],
- .rt7 = mrt_comp[7]));
+ A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
- tu_cs_emit_regs(cs,
- A6XX_SP_FS_RENDER_COMPONENTS(
- .rt0 = mrt_comp[0],
- .rt1 = mrt_comp[1],
- .rt2 = mrt_comp[2],
- .rt3 = mrt_comp[3],
- .rt4 = mrt_comp[4],
- .rt5 = mrt_comp[5],
- .rt6 = mrt_comp[6],
- .rt7 = mrt_comp[7]));
-
- // XXX: We probably can't hardcode LAYER_CNTL_TYPE.
- tu_cs_emit_regs(cs,
- A6XX_GRAS_LAYER_CNTL(.layered = fb->layers > 1,
- .type = LAYER_2D_ARRAY));
+ tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(fb->layers - 1));
}
-static void
-tu6_emit_msaa(struct tu_cmd_buffer *cmd,
- const struct tu_subpass *subpass,
- struct tu_cs *cs)
+void
+tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples)
{
- const enum a3xx_msaa_samples samples = tu_msaa_samples(subpass->samples);
+ const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
bool msaa_disable = samples == MSAA_ONE;
tu_cs_emit_regs(cs,
continue;
const struct tu_image_view *iview = fb->attachments[a].attachment;
- if (iview->image->layout.ubwc_layer_size != 0)
+ if (iview->ubwc_enabled)
mrts_ubwc_enable |= 1 << i;
}
const uint32_t a = subpass->depth_stencil_attachment.attachment;
if (a != VK_ATTACHMENT_UNUSED) {
const struct tu_image_view *iview = fb->attachments[a].attachment;
- if (iview->image->layout.ubwc_layer_size != 0)
+ if (iview->ubwc_enabled)
cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
}
uint32_t x2 = x1 + render_area->extent.width - 1;
uint32_t y2 = y1 + render_area->extent.height - 1;
- /* TODO: alignment requirement seems to be less than tile_align_w/h */
if (align) {
- x1 = x1 & ~cmd->device->physical_device->tile_align_w;
- y1 = y1 & ~cmd->device->physical_device->tile_align_h;
- x2 = ALIGN_POT(x2 + 1, cmd->device->physical_device->tile_align_w) - 1;
- y2 = ALIGN_POT(y2 + 1, cmd->device->physical_device->tile_align_h) - 1;
+ x1 = x1 & ~(GMEM_ALIGN_W - 1);
+ y1 = y1 & ~(GMEM_ALIGN_H - 1);
+ x2 = ALIGN_POT(x2 + 1, GMEM_ALIGN_W) - 1;
+ y2 = ALIGN_POT(y2 + 1, GMEM_ALIGN_H) - 1;
}
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
}
-static void
-tu6_emit_blit_info(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- const struct tu_image_view *iview,
- uint32_t gmem_offset,
- bool resolve)
-{
- tu_cs_emit_regs(cs,
- A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
-
- const struct tu_native_format format =
- tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
-
- enum a6xx_tile_mode tile_mode =
- tu6_get_image_tile_mode(iview->image, iview->base_mip);
- tu_cs_emit_regs(cs,
- A6XX_RB_BLIT_DST_INFO(
- .tile_mode = tile_mode,
- .samples = tu_msaa_samples(iview->image->samples),
- .color_format = format.fmt,
- .color_swap = format.swap,
- .flags = iview->image->layout.ubwc_layer_size != 0),
- A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
- A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
- A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
-
- if (iview->image->layout.ubwc_layer_size) {
- tu_cs_emit_regs(cs,
- A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
- A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
- }
-
- tu_cs_emit_regs(cs,
- A6XX_RB_BLIT_BASE_GMEM(gmem_offset));
-}
-
-static void
-tu6_emit_blit(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
-{
- tu6_emit_event_write(cmd, cs, BLIT, false);
-}
-
-static void
-tu6_emit_window_scissor(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
+void
+tu6_emit_window_scissor(struct tu_cs *cs,
uint32_t x1,
uint32_t y1,
uint32_t x2,
A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
}
-static void
-tu6_emit_window_offset(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- uint32_t x1,
- uint32_t y1)
+void
+tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
{
tu_cs_emit_regs(cs,
A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
if (!cmd->state.pass->gmem_pixels)
return true;
+ if (cmd->state.framebuffer->layers > 1)
+ return true;
+
return cmd->state.tiling_config.force_sysmem;
}
const uint32_t y1 = tile->begin.y;
const uint32_t x2 = tile->end.x - 1;
const uint32_t y2 = tile->end.y - 1;
- tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
- tu6_emit_window_offset(cmd, cs, x1, y1);
+ tu6_emit_window_scissor(cs, x1, y1, x2, y2);
+ tu6_emit_window_offset(cs, x1, y1);
tu_cs_emit_regs(cs,
A6XX_VPC_SO_OVERRIDE(.so_disable = false));
tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
- tu_cs_emit_qw(cs, cmd->vsc_data.iova + tile->pipe * cmd->vsc_data_pitch);
- tu_cs_emit_qw(cs, cmd->vsc_data.iova + (tile->pipe * 4) + (32 * cmd->vsc_data_pitch));
- tu_cs_emit_qw(cs, cmd->vsc_data2.iova + (tile->pipe * cmd->vsc_data2_pitch));
+ tu_cs_emit_qw(cs, cmd->vsc_draw_strm.iova + tile->pipe * cmd->vsc_draw_strm_pitch);
+ tu_cs_emit_qw(cs, cmd->vsc_draw_strm.iova + (tile->pipe * 4) + (32 * cmd->vsc_draw_strm_pitch));
+ tu_cs_emit_qw(cs, cmd->vsc_prim_strm.iova + (tile->pipe * cmd->vsc_prim_strm_pitch));
tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
tu_cs_emit(cs, 0x0);
tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
tu_cs_emit(cs, 0x0);
-
- tu_cs_emit_regs(cs,
- A6XX_RB_UNKNOWN_8804(0));
-
- tu_cs_emit_regs(cs,
- A6XX_SP_TP_UNKNOWN_B304(0));
-
- tu_cs_emit_regs(cs,
- A6XX_GRAS_UNKNOWN_80A4(0));
} else {
tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
tu_cs_emit(cs, 0x1);
}
}
-static void
-tu6_emit_load_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a)
-{
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
- const struct tu_framebuffer *fb = cmd->state.framebuffer;
- const struct tu_image_view *iview = fb->attachments[a].attachment;
- const struct tu_render_pass_attachment *attachment =
- &cmd->state.pass->attachments[a];
-
- if (attachment->gmem_offset < 0)
- return;
-
- const uint32_t x1 = tiling->render_area.offset.x;
- const uint32_t y1 = tiling->render_area.offset.y;
- const uint32_t x2 = x1 + tiling->render_area.extent.width;
- const uint32_t y2 = y1 + tiling->render_area.extent.height;
- const uint32_t tile_x2 =
- tiling->tile0.offset.x + tiling->tile0.extent.width * tiling->tile_count.width;
- const uint32_t tile_y2 =
- tiling->tile0.offset.y + tiling->tile0.extent.height * tiling->tile_count.height;
- bool need_load =
- x1 != tiling->tile0.offset.x || x2 != MIN2(fb->width, tile_x2) ||
- y1 != tiling->tile0.offset.y || y2 != MIN2(fb->height, tile_y2);
-
- if (need_load)
- tu_finishme("improve handling of unaligned render area");
-
- if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
- need_load = true;
-
- if (vk_format_has_stencil(iview->vk_format) &&
- attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD)
- need_load = true;
-
- if (need_load) {
- tu6_emit_blit_info(cmd, cs, iview, attachment->gmem_offset, false);
- tu6_emit_blit(cmd, cs);
- }
-}
-
-static void
-tu6_emit_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
- uint32_t a,
- const VkRenderPassBeginInfo *info)
-{
- const struct tu_framebuffer *fb = cmd->state.framebuffer;
- const struct tu_image_view *iview = fb->attachments[a].attachment;
- const struct tu_render_pass_attachment *attachment =
- &cmd->state.pass->attachments[a];
- unsigned clear_mask = 0;
-
- /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
- if (attachment->gmem_offset < 0)
- return;
-
- if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
- clear_mask = 0xf;
-
- if (vk_format_has_stencil(iview->vk_format)) {
- clear_mask &= 0x1;
- if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
- clear_mask |= 0x2;
- }
- if (!clear_mask)
- return;
-
- tu_clear_gmem_attachment(cmd, cs, a, clear_mask,
- &info->pClearValues[a]);
-}
-
-static void
-tu6_emit_predicated_blit(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- uint32_t a,
- uint32_t gmem_a,
- bool resolve)
-{
- tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
-
- tu6_emit_blit_info(cmd, cs,
- cmd->state.framebuffer->attachments[a].attachment,
- cmd->state.pass->attachments[gmem_a].gmem_offset, resolve);
- tu6_emit_blit(cmd, cs);
-
- tu_cond_exec_end(cs);
-}
-
static void
tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
uint32_t gmem_a)
{
const struct tu_framebuffer *fb = cmd->state.framebuffer;
- const struct tu_image_view *dst = fb->attachments[a].attachment;
- const struct tu_image_view *src = fb->attachments[gmem_a].attachment;
-
- tu_blit(cmd, cs, &(struct tu_blit) {
- .dst = sysmem_attachment_surf(dst, dst->base_layer,
- &cmd->state.tiling_config.render_area),
- .src = sysmem_attachment_surf(src, src->base_layer,
- &cmd->state.tiling_config.render_area),
- .layers = fb->layers,
- });
-}
-
+ struct tu_image_view *dst = fb->attachments[a].attachment;
+ struct tu_image_view *src = fb->attachments[gmem_a].attachment;
-/* Emit a MSAA resolve operation, with both gmem and sysmem paths. */
-static void tu6_emit_resolve(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- uint32_t a,
- uint32_t gmem_a)
-{
- if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
- return;
-
- tu6_emit_predicated_blit(cmd, cs, a, gmem_a, true);
-
- tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
- tu6_emit_sysmem_resolve(cmd, cs, a, gmem_a);
- tu_cond_exec_end(cs);
+ tu_resolve_sysmem(cmd, cs, src, dst, fb->layers, &cmd->state.tiling_config.render_area);
}
static void
-tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- uint32_t a,
- uint32_t gmem_a)
+tu6_emit_sysmem_resolves(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ const struct tu_subpass *subpass)
{
- if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
- return;
+ if (subpass->resolve_attachments) {
+ /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
+ * Commands":
+ *
+ * End-of-subpass multisample resolves are treated as color
+ * attachment writes for the purposes of synchronization. That is,
+ * they are considered to execute in the
+ * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
+ * their writes are synchronized with
+ * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
+ * rendering within a subpass and any resolve operations at the end
+ * of the subpass occurs automatically, without need for explicit
+ * dependencies or pipeline barriers. However, if the resolve
+ * attachment is also used in a different subpass, an explicit
+ * dependency is needed.
+ *
+ * We use the CP_BLIT path for sysmem resolves, which is really a
+ * transfer command, so we have to manually flush similar to the gmem
+ * resolve case. However, a flush afterwards isn't needed because of the
+ * last sentence and the fact that we're in sysmem mode.
+ */
+ tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS);
+ tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
+
+ /* Wait for the flushes to land before using the 2D engine */
+ tu_cs_emit_wfi(cs);
+
+ for (unsigned i = 0; i < subpass->color_count; i++) {
+ uint32_t a = subpass->resolve_attachments[i].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
- tu6_emit_blit_info(cmd, cs,
- cmd->state.framebuffer->attachments[a].attachment,
- cmd->state.pass->attachments[gmem_a].gmem_offset, true);
- tu6_emit_blit(cmd, cs);
+ tu6_emit_sysmem_resolve(cmd, cs, a,
+ subpass->color_attachments[i].attachment);
+ }
+ }
}
static void
for (uint32_t a = 0; a < pass->attachment_count; ++a) {
if (pass->attachments[a].gmem_offset >= 0)
- tu6_emit_store_attachment(cmd, cs, a, a);
+ tu_store_gmem_attachment(cmd, cs, a, a);
}
if (subpass->resolve_attachments) {
for (unsigned i = 0; i < subpass->color_count; i++) {
uint32_t a = subpass->resolve_attachments[i].attachment;
if (a != VK_ATTACHMENT_UNUSED)
- tu6_emit_store_attachment(cmd, cs, a,
- subpass->color_attachments[i].attachment);
+ tu_store_gmem_attachment(cmd, cs, a,
+ subpass->color_attachments[i].attachment);
}
}
}
static void
tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
- tu6_emit_cache_flush(cmd, cs);
+ const struct tu_physical_device *phys_dev = cmd->device->physical_device;
+
+ tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, A6XX_RB_CCU_CNTL_OFFSET(0x20000));
+ tu_cs_emit_regs(cs,
+ A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
+ cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, 1);
+ tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236,
+ A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
- tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B304, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8804, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A4, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A5, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A6, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8805, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8806, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
tu_cs_sanity_check(cs);
}
-static void
-tu6_cache_flush(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
-{
- unsigned seqno;
-
- seqno = tu6_emit_event_write(cmd, cs, RB_DONE_TS, true);
-
- tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
- tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
- CP_WAIT_REG_MEM_0_POLL_MEMORY);
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
- tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(seqno));
- tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0));
- tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
-
- seqno = tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
-
- tu_cs_emit_pkt7(cs, CP_WAIT_MEM_GTE, 4);
- tu_cs_emit(cs, CP_WAIT_MEM_GTE_0_RESERVED(0));
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
- tu_cs_emit(cs, CP_WAIT_MEM_GTE_3_REF(seqno));
-}
-
static void
update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
tu_cs_emit_regs(cs,
A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
.height = tiling->tile0.extent.height),
- A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
- .bo_offset = 32 * cmd->vsc_data_pitch));
+ A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = &cmd->vsc_draw_strm,
+ .bo_offset = 32 * cmd->vsc_draw_strm_pitch));
tu_cs_emit_regs(cs,
A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
tu_cs_emit(cs, tiling->pipe_config[i]);
tu_cs_emit_regs(cs,
- A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = &cmd->vsc_data2),
- A6XX_VSC_PIPE_DATA2_PITCH(cmd->vsc_data2_pitch),
- A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(cmd->vsc_data2.size));
+ A6XX_VSC_PRIM_STRM_ADDRESS(.bo = &cmd->vsc_prim_strm),
+ A6XX_VSC_PRIM_STRM_PITCH(cmd->vsc_prim_strm_pitch),
+ A6XX_VSC_PRIM_STRM_ARRAY_PITCH(cmd->vsc_prim_strm.size));
tu_cs_emit_regs(cs,
- A6XX_VSC_PIPE_DATA_ADDRESS(.bo = &cmd->vsc_data),
- A6XX_VSC_PIPE_DATA_PITCH(cmd->vsc_data_pitch),
- A6XX_VSC_PIPE_DATA_ARRAY_PITCH(cmd->vsc_data.size));
+ A6XX_VSC_DRAW_STRM_ADDRESS(.bo = &cmd->vsc_draw_strm),
+ A6XX_VSC_DRAW_STRM_PITCH(cmd->vsc_draw_strm_pitch),
+ A6XX_VSC_DRAW_STRM_ARRAY_PITCH(cmd->vsc_draw_strm.size));
}
static void
tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
- tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
+ tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
- tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data_pitch));
+ tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch));
tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
- tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_data_pitch));
+ tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_draw_strm_pitch));
tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
- tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
+ tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
- tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_data2_pitch));
+ tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch));
tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
- tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_data2_pitch));
+ tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_prim_strm_pitch));
}
tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
* if (b0 set)..
*/
- /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
+ /* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
A6XX_CP_REG_TEST_0_BIT(0) |
uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
- tu6_emit_window_scissor(cmd, cs, x1, y1, x2, y2);
+ tu6_emit_window_scissor(cs, x1, y1, x2, y2);
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, UNK_2D);
- tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
- tu6_cache_flush(cmd, cs);
+ /* This flush is probably required because the VSC, which produces the
+ * visibility stream, is a client of UCHE, whereas the CP needs to read the
+ * visibility stream (without caching) to do draw skipping. The
+ * WFI+WAIT_FOR_ME combination guarantees that the binning commands
+ * submitted are finished before reading the VSC regs (in
+ * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
+ * part of draws).
+ */
+ tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS);
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
tu_cs_emit(cs, 0x0);
-
- tu_cs_emit_wfi(cs);
-
- tu_cs_emit_regs(cs,
- A6XX_RB_CCU_CNTL(.dword = phys_dev->magic.RB_CCU_CNTL_gmem));
-
- cmd->wait_for_idle = false;
-}
-
-static void
-tu_emit_sysmem_clear_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
- uint32_t a,
- const VkRenderPassBeginInfo *info)
-{
- const struct tu_framebuffer *fb = cmd->state.framebuffer;
- const struct tu_image_view *iview = fb->attachments[a].attachment;
- const struct tu_render_pass_attachment *attachment =
- &cmd->state.pass->attachments[a];
- unsigned clear_mask = 0;
-
- /* note: this means it isn't used by any subpass and shouldn't be cleared anyway */
- if (attachment->gmem_offset < 0)
- return;
-
- if (attachment->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
- clear_mask = 0xf;
- }
-
- if (vk_format_has_stencil(iview->vk_format)) {
- clear_mask &= 0x1;
- if (attachment->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR)
- clear_mask |= 0x2;
- if (clear_mask != 0x3)
- tu_finishme("depth/stencil only load op");
- }
-
- if (!clear_mask)
- return;
-
- tu_clear_sysmem_attachment(cmd, cs, a,
- &info->pClearValues[a], &(struct VkClearRect) {
- .rect = info->renderArea,
- .baseArrayLayer = iview->base_layer,
- .layerCount = iview->layer_count,
- });
}
static void
tu6_emit_blit_scissor(cmd, cs, true);
for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
- tu6_emit_load_attachment(cmd, cs, i);
+ tu_load_gmem_attachment(cmd, cs, i, false);
tu6_emit_blit_scissor(cmd, cs, false);
for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
- tu6_emit_clear_attachment(cmd, cs, i, info);
+ tu_clear_gmem_attachment(cmd, cs, i, info);
tu_cond_exec_end(cs);
- /* invalidate because reading input attachments will cache GMEM and
- * the cache isn''t updated when GMEM is written
- * TODO: is there a no-cache bit for textures?
- */
- if (cmd->state.subpass->input_count)
- tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
-
tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
- tu_emit_sysmem_clear_attachment(cmd, cs, i, info);
+ tu_clear_sysmem_attachment(cmd, cs, i, info);
tu_cond_exec_end(cs);
}
const struct tu_framebuffer *fb = cmd->state.framebuffer;
assert(fb->width > 0 && fb->height > 0);
- tu6_emit_window_scissor(cmd, cs, 0, 0, fb->width - 1, fb->height - 1);
- tu6_emit_window_offset(cmd, cs, 0, 0);
+ tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
+ tu6_emit_window_offset(cs, 0, 0);
tu6_emit_bin_size(cs, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
- tu6_emit_lrz_flush(cmd, cs);
+ tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
tu_cs_emit(cs, 0x0);
- tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_COLOR, false);
- tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH, false);
- tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
-
- tu6_emit_wfi(cmd, cs);
- tu_cs_emit_regs(cs,
- A6XX_RB_CCU_CNTL(.offset = 0x20000));
+ tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
/* enable stream-out, with sysmem there is only one pass: */
tu_cs_emit_regs(cs,
/* Do any resolves of the last subpass. These are handled in the
* tile_store_ib in the gmem path.
*/
-
- const struct tu_subpass *subpass = cmd->state.subpass;
- if (subpass->resolve_attachments) {
- for (unsigned i = 0; i < subpass->color_count; i++) {
- uint32_t a = subpass->resolve_attachments[i].attachment;
- if (a != VK_ATTACHMENT_UNUSED)
- tu6_emit_sysmem_resolve(cmd, cs, a,
- subpass->color_attachments[i].attachment);
- }
- }
+ tu6_emit_sysmem_resolves(cmd, cs, cmd->state.subpass);
tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
tu_cs_emit(cs, 0x0);
- tu6_emit_lrz_flush(cmd, cs);
-
- tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
- tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
+ tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
tu_cs_sanity_check(cs);
}
{
struct tu_physical_device *phys_dev = cmd->device->physical_device;
- tu6_emit_lrz_flush(cmd, cs);
+ tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
/* lrz clear? */
- tu6_emit_cache_flush(cmd, cs);
-
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
tu_cs_emit(cs, 0x0);
- /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
- tu6_emit_wfi(cmd, cs);
- tu_cs_emit_regs(cs,
- A6XX_RB_CCU_CNTL(.dword = phys_dev->magic.RB_CCU_CNTL_gmem));
+ tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_GMEM);
const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
if (use_hw_binning(cmd)) {
tu6_emit_tile_select(cmd, cs, tile);
tu_cs_emit_call(cs, &cmd->draw_cs);
- cmd->wait_for_idle = true;
if (use_hw_binning(cmd)) {
tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
tu_cs_emit_regs(cs,
A6XX_GRAS_LRZ_CNTL(0));
- tu6_emit_lrz_flush(cmd, cs);
+ tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
- tu6_emit_event_write(cmd, cs, CACHE_FLUSH_TS, true);
+ tu6_emit_event_write(cmd, cs, PC_CCU_RESOLVE_TS);
tu_cs_sanity_check(cs);
}
tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
- cmd->wait_for_idle = true;
tu6_sysmem_render_end(cmd, &cmd->cs);
}
static void
tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer *cmd)
{
- const uint32_t tile_store_space = 32 + 23 * cmd->state.pass->attachment_count;
+ const uint32_t tile_store_space = 11 + (35 * 2) * cmd->state.pass->attachment_count;
struct tu_cs sub_cs;
VkResult result =
struct tu_tiling_config *tiling = &cmd->state.tiling_config;
tiling->render_area = *render_area;
- tiling->force_sysmem = force_sysmem(cmd, render_area);
+ tiling->force_sysmem = false;
- tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
+ tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass);
tu_tiling_config_update_pipe_layout(tiling, dev);
tu_tiling_config_update_pipes(tiling, dev);
}
goto fail_scratch_bo;
/* TODO: resize on overflow */
- cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
- cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
- cmd_buffer->vsc_data = device->vsc_data;
- cmd_buffer->vsc_data2 = device->vsc_data2;
+ cmd_buffer->vsc_draw_strm_pitch = device->vsc_draw_strm_pitch;
+ cmd_buffer->vsc_prim_strm_pitch = device->vsc_prim_strm_pitch;
+ cmd_buffer->vsc_draw_strm = device->vsc_draw_strm;
+ cmd_buffer->vsc_prim_strm = device->vsc_prim_strm;
return VK_SUCCESS;
list_del(&cmd_buffer->pool_link);
- for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
+ for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
tu_cs_finish(&cmd_buffer->cs);
static VkResult
tu_reset_cmd_buffer(struct tu_cmd_buffer *cmd_buffer)
{
- cmd_buffer->wait_for_idle = true;
-
cmd_buffer->record_result = VK_SUCCESS;
tu_bo_list_reset(&cmd_buffer->bo_list);
tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
tu_cs_reset(&cmd_buffer->sub_cs);
- for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
+ for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
cmd_buffer->descriptors[i].valid = 0;
cmd_buffer->descriptors[i].push_dirty = false;
}
return tu_reset_cmd_buffer(cmd_buffer);
}
+/* Initialize the cache, assuming all necessary flushes have happened but *not*
+ * invalidations.
+ */
+static void
+tu_cache_init(struct tu_cache_state *cache)
+{
+ cache->flush_bits = 0;
+ cache->pending_flush_bits = TU_CMD_FLAG_ALL_INVALIDATE;
+}
+
VkResult
tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
const VkCommandBufferBeginInfo *pBeginInfo)
}
memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
+ tu_cache_init(&cmd_buffer->state.cache);
+ tu_cache_init(&cmd_buffer->state.renderpass_cache);
cmd_buffer->usage_flags = pBeginInfo->flags;
tu_cs_begin(&cmd_buffer->cs);
tu_cs_begin(&cmd_buffer->draw_cs);
tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
- cmd_buffer->scratch_seqno = 0;
-
/* setup initial configuration into command buffer */
if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
switch (cmd_buffer->queue_family_index) {
default:
break;
}
- } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
- (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
- assert(pBeginInfo->pInheritanceInfo);
- cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
- cmd_buffer->state.subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
+ } else if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
+ if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
+ assert(pBeginInfo->pInheritanceInfo);
+ cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
+ cmd_buffer->state.subpass =
+ &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
+ } else {
+ /* When executing in the middle of another command buffer, the CCU
+ * state is unknown.
+ */
+ cmd_buffer->state.ccu_state = TU_CMD_CCU_UNKNOWN;
+ }
}
cmd_buffer->status = TU_CMD_BUFFER_STATUS_RECORDING;
return VK_SUCCESS;
}
+/* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
+ * rendering can skip over unused state), so we need to collect all the
+ * bindings together into a single state emit at draw time.
+ */
void
tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
uint32_t firstBinding,
assert(firstBinding + bindingCount <= MAX_VBS);
for (uint32_t i = 0; i < bindingCount; i++) {
- cmd->state.vb.buffers[firstBinding + i] =
- tu_buffer_from_handle(pBuffers[i]);
+ struct tu_buffer *buf = tu_buffer_from_handle(pBuffers[i]);
+
+ cmd->state.vb.buffers[firstBinding + i] = buf;
cmd->state.vb.offsets[firstBinding + i] = pOffsets[i];
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
}
- /* VB states depend on VkPipelineVertexInputStateCreateInfo */
cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
}
descriptors_state->sets[idx] = set;
descriptors_state->valid |= (1u << idx);
+ /* Note: the actual input attachment indices come from the shader
+ * itself, so we can't generate the patched versions of these until
+ * draw time when both the pipeline and descriptors are bound and
+ * we're inside the render pass.
+ */
+ unsigned dst_idx = layout->set[idx].input_attachment_start;
+ memcpy(&descriptors_state->input_attachments[dst_idx * A6XX_TEX_CONST_DWORDS],
+ set->dynamic_descriptors,
+ set->layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
+
for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
- unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
+ /* Dynamic buffers come after input attachments in the descriptor set
+ * itself, but due to how the Vulkan descriptor set binding works, we
+ * have to put input attachments and dynamic buffers in separate
+ * buffers in the descriptor_state and then combine them at draw
+ * time. Binding a descriptor set only invalidates the descriptor
+ * sets after it, but if we try to tightly pack the descriptors after
+ * the input attachments then we could corrupt dynamic buffers in the
+ * descriptor set before it, or we'd have to move all the dynamic
+ * buffers over. We just put them into separate buffers to make
+ * binding as well as the later patching of input attachments easy.
+ */
+ unsigned src_idx = j + set->layout->input_attachment_count;
+ unsigned dst_idx = j + layout->set[idx].dynamic_offset_start;
assert(dyn_idx < dynamicOffsetCount);
- descriptors_state->dynamic_buffers[idx] =
- set->dynamic_descriptors[j].va + pDynamicOffsets[dyn_idx];
+ uint32_t *dst =
+ &descriptors_state->dynamic_descriptors[dst_idx * A6XX_TEX_CONST_DWORDS];
+ uint32_t *src =
+ &set->dynamic_descriptors[src_idx * A6XX_TEX_CONST_DWORDS];
+ uint32_t offset = pDynamicOffsets[dyn_idx];
+
+ /* Patch the storage/uniform descriptors right away. */
+ if (layout->set[idx].layout->dynamic_ubo & (1 << j)) {
+ /* Note: we can assume here that the addition won't roll over and
+ * change the SIZE field.
+ */
+ uint64_t va = src[0] | ((uint64_t)src[1] << 32);
+ va += offset;
+ dst[0] = va;
+ dst[1] = va >> 32;
+ } else {
+ memcpy(dst, src, A6XX_TEX_CONST_DWORDS * 4);
+ /* Note: A6XX_IBO_5_DEPTH is always 0 */
+ uint64_t va = dst[4] | ((uint64_t)dst[5] << 32);
+ va += offset;
+ dst[4] = va;
+ dst[5] = va >> 32;
+ }
}
}
- cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
+ if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE)
+ cmd_buffer->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
+ else
+ cmd_buffer->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
}
void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
cmd->state.dirty |= TU_CMD_DIRTY_PUSH_CONSTANTS;
}
+/* Flush everything which has been made available but we haven't actually
+ * flushed yet.
+ */
+static void
+tu_flush_all_pending(struct tu_cache_state *cache)
+{
+ cache->flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
+ cache->pending_flush_bits &= ~TU_CMD_FLAG_ALL_FLUSH;
+}
+
VkResult
tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
- if (cmd_buffer->scratch_seqno) {
- tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
- MSM_SUBMIT_BO_WRITE);
+ /* We currently flush CCU at the end of the command buffer, like
+ * what the blob does. There's implicit synchronization around every
+ * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
+ * know yet if this command buffer will be the last in the submit so we
+ * have to defensively flush everything else.
+ *
+ * TODO: We could definitely do better than this, since these flushes
+ * aren't required by Vulkan, but we'd need kernel support to do that.
+ * Ideally, we'd like the kernel to flush everything afterwards, so that we
+ * wouldn't have to do any flushes here, and when submitting multiple
+ * command buffers there wouldn't be any unnecessary flushes in between.
+ */
+ if (cmd_buffer->state.pass) {
+ tu_flush_all_pending(&cmd_buffer->state.renderpass_cache);
+ tu_emit_cache_flush_renderpass(cmd_buffer, &cmd_buffer->draw_cs);
+ } else {
+ tu_flush_all_pending(&cmd_buffer->state.cache);
+ cmd_buffer->state.cache.flush_bits |=
+ TU_CMD_FLAG_CCU_FLUSH_COLOR |
+ TU_CMD_FLAG_CCU_FLUSH_DEPTH;
+ tu_emit_cache_flush(cmd_buffer, &cmd_buffer->cs);
}
+ tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
+ MSM_SUBMIT_BO_WRITE);
+
if (cmd_buffer->use_vsc_data) {
- tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data,
+ tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_draw_strm,
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
- tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_data2,
+ tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_prim_strm,
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
}
break;
}
+ /* If the new pipeline requires more VBs than we had previously set up, we
+ * need to re-emit them in SDS. If it requires the same set or fewer, we
+ * can just re-use the old SDS.
+ */
+ if (pipeline->vi.bindings_used & ~cmd->vertex_bindings_set)
+ cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
+
tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
const VkViewport *pViewports)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- struct tu_cs *draw_cs = &cmd->draw_cs;
assert(firstViewport == 0 && viewportCount == 1);
- tu6_emit_viewport(draw_cs, pViewports);
-
- tu_cs_sanity_check(draw_cs);
+ cmd->state.dynamic.viewport.viewports[0] = pViewports[0];
+ cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_VIEWPORT;
}
void
const VkRect2D *pScissors)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- struct tu_cs *draw_cs = &cmd->draw_cs;
assert(firstScissor == 0 && scissorCount == 1);
- tu6_emit_scissor(draw_cs, pScissors);
-
- tu_cs_sanity_check(draw_cs);
+ cmd->state.dynamic.scissor.scissors[0] = pScissors[0];
+ cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_SCISSOR;
}
void
}
void
-tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
- uint32_t commandBufferCount,
- const VkCommandBuffer *pCmdBuffers)
+tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer,
+ const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- VkResult result;
- assert(commandBufferCount > 0);
+ tu6_emit_sample_locations(&cmd->draw_cs, pSampleLocationsInfo);
+}
- for (uint32_t i = 0; i < commandBufferCount; i++) {
- TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
+static void
+tu_flush_for_access(struct tu_cache_state *cache,
+ enum tu_cmd_access_mask src_mask,
+ enum tu_cmd_access_mask dst_mask)
+{
+ enum tu_cmd_flush_bits flush_bits = 0;
+
+ if (src_mask & TU_ACCESS_SYSMEM_WRITE) {
+ cache->pending_flush_bits |= TU_CMD_FLAG_ALL_INVALIDATE;
+ }
+
+#define SRC_FLUSH(domain, flush, invalidate) \
+ if (src_mask & TU_ACCESS_##domain##_WRITE) { \
+ cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
+ (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
+ }
+
+ SRC_FLUSH(UCHE, CACHE_FLUSH, CACHE_INVALIDATE)
+ SRC_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
+ SRC_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
+
+#undef SRC_FLUSH
+
+#define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
+ if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
+ flush_bits |= TU_CMD_FLAG_##flush; \
+ cache->pending_flush_bits |= \
+ (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
+ }
+
+ SRC_INCOHERENT_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
+ SRC_INCOHERENT_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
+
+#undef SRC_INCOHERENT_FLUSH
+
+ if (dst_mask & (TU_ACCESS_SYSMEM_READ | TU_ACCESS_SYSMEM_WRITE)) {
+ flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
+ }
+
+#define DST_FLUSH(domain, flush, invalidate) \
+ if (dst_mask & (TU_ACCESS_##domain##_READ | \
+ TU_ACCESS_##domain##_WRITE)) { \
+ flush_bits |= cache->pending_flush_bits & \
+ (TU_CMD_FLAG_##invalidate | \
+ (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
+ }
+
+ DST_FLUSH(UCHE, CACHE_FLUSH, CACHE_INVALIDATE)
+ DST_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
+ DST_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
+
+#undef DST_FLUSH
+
+#define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
+ if (dst_mask & (TU_ACCESS_##domain##_READ | \
+ TU_ACCESS_##domain##_WRITE)) { \
+ flush_bits |= TU_CMD_FLAG_##invalidate | \
+ (cache->pending_flush_bits & \
+ (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
+ }
+
+ DST_INCOHERENT_FLUSH(CCU_COLOR, CCU_FLUSH_COLOR, CCU_INVALIDATE_COLOR)
+ DST_INCOHERENT_FLUSH(CCU_DEPTH, CCU_FLUSH_DEPTH, CCU_INVALIDATE_DEPTH)
+
+#undef DST_INCOHERENT_FLUSH
+
+ if (dst_mask & TU_ACCESS_WFI_READ) {
+ flush_bits |= TU_CMD_FLAG_WFI;
+ }
+
+ cache->flush_bits |= flush_bits;
+ cache->pending_flush_bits &= ~flush_bits;
+}
+
+static enum tu_cmd_access_mask
+vk2tu_access(VkAccessFlags flags, bool gmem)
+{
+ enum tu_cmd_access_mask mask = 0;
+
+ /* If the GPU writes a buffer that is then read by an indirect draw
+ * command, we theoretically need a WFI + WAIT_FOR_ME combination to
+ * wait for the writes to complete. The WAIT_FOR_ME is performed as part
+ * of the draw by the firmware, so we just need to execute a WFI.
+ */
+ if (flags &
+ (VK_ACCESS_INDIRECT_COMMAND_READ_BIT |
+ VK_ACCESS_MEMORY_READ_BIT)) {
+ mask |= TU_ACCESS_WFI_READ;
+ }
+
+ if (flags &
+ (VK_ACCESS_INDIRECT_COMMAND_READ_BIT | /* Read performed by CP */
+ VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT | /* Read performed by CP, I think */
+ VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT | /* Read performed by CP */
+ VK_ACCESS_HOST_READ_BIT | /* sysmem by definition */
+ VK_ACCESS_MEMORY_READ_BIT)) {
+ mask |= TU_ACCESS_SYSMEM_READ;
+ }
+
+ if (flags &
+ (VK_ACCESS_HOST_WRITE_BIT |
+ VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT | /* Write performed by CP, I think */
+ VK_ACCESS_MEMORY_WRITE_BIT)) {
+ mask |= TU_ACCESS_SYSMEM_WRITE;
+ }
+
+ if (flags &
+ (VK_ACCESS_INDEX_READ_BIT | /* Read performed by PC, I think */
+ VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | /* Read performed by VFD */
+ VK_ACCESS_UNIFORM_READ_BIT | /* Read performed by SP */
+ /* TODO: Is there a no-cache bit for textures so that we can ignore
+ * these?
+ */
+ VK_ACCESS_INPUT_ATTACHMENT_READ_BIT | /* Read performed by TP */
+ VK_ACCESS_SHADER_READ_BIT | /* Read perfomed by SP/TP */
+ VK_ACCESS_MEMORY_READ_BIT)) {
+ mask |= TU_ACCESS_UCHE_READ;
+ }
+
+ if (flags &
+ (VK_ACCESS_SHADER_WRITE_BIT | /* Write performed by SP */
+ VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT | /* Write performed by VPC */
+ VK_ACCESS_MEMORY_WRITE_BIT)) {
+ mask |= TU_ACCESS_UCHE_WRITE;
+ }
+
+ /* When using GMEM, the CCU is always flushed automatically to GMEM, and
+ * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
+ * previous writes in sysmem mode when transitioning to GMEM. Therefore we
+ * can ignore CCU and pretend that color attachments and transfers use
+ * sysmem directly.
+ */
+
+ if (flags &
+ (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT |
+ VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT |
+ VK_ACCESS_MEMORY_READ_BIT)) {
+ if (gmem)
+ mask |= TU_ACCESS_SYSMEM_READ;
+ else
+ mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_READ;
+ }
+
+ if (flags &
+ (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT |
+ VK_ACCESS_MEMORY_READ_BIT)) {
+ if (gmem)
+ mask |= TU_ACCESS_SYSMEM_READ;
+ else
+ mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ;
+ }
+
+ if (flags &
+ (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT |
+ VK_ACCESS_MEMORY_WRITE_BIT)) {
+ if (gmem) {
+ mask |= TU_ACCESS_SYSMEM_WRITE;
+ } else {
+ mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
+ }
+ }
+
+ if (flags &
+ (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT |
+ VK_ACCESS_MEMORY_WRITE_BIT)) {
+ if (gmem) {
+ mask |= TU_ACCESS_SYSMEM_WRITE;
+ } else {
+ mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
+ }
+ }
+
+ /* When the dst access is a transfer read/write, it seems we sometimes need
+ * to insert a WFI after any flushes, to guarantee that the flushes finish
+ * before the 2D engine starts. However the opposite (i.e. a WFI after
+ * CP_BLIT and before any subsequent flush) does not seem to be needed, and
+ * the blob doesn't emit such a WFI.
+ */
+
+ if (flags &
+ (VK_ACCESS_TRANSFER_WRITE_BIT |
+ VK_ACCESS_MEMORY_WRITE_BIT)) {
+ if (gmem) {
+ mask |= TU_ACCESS_SYSMEM_WRITE;
+ } else {
+ mask |= TU_ACCESS_CCU_COLOR_WRITE;
+ }
+ mask |= TU_ACCESS_WFI_READ;
+ }
+
+ if (flags &
+ (VK_ACCESS_TRANSFER_READ_BIT | /* Access performed by TP */
+ VK_ACCESS_MEMORY_READ_BIT)) {
+ mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_WFI_READ;
+ }
+
+ return mask;
+}
+
+
+void
+tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
+ uint32_t commandBufferCount,
+ const VkCommandBuffer *pCmdBuffers)
+{
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ VkResult result;
+
+ assert(commandBufferCount > 0);
+
+ /* Emit any pending flushes. */
+ if (cmd->state.pass) {
+ tu_flush_all_pending(&cmd->state.renderpass_cache);
+ tu_emit_cache_flush_renderpass(cmd, &cmd->draw_cs);
+ } else {
+ tu_flush_all_pending(&cmd->state.cache);
+ tu_emit_cache_flush(cmd, &cmd->cs);
+ }
+
+ for (uint32_t i = 0; i < commandBufferCount; i++) {
+ TU_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
result = tu_bo_list_merge(&cmd->bo_list, &secondary->bo_list);
if (result != VK_SUCCESS) {
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
}
- tu_cs_emit_call(&cmd->cs, &secondary->cs);
+ tu_cs_add_entries(&cmd->cs, &secondary->cs);
}
}
cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
+
+ /* After executing secondary command buffers, there may have been arbitrary
+ * flushes executed, so when we encounter a pipeline barrier with a
+ * srcMask, we have to assume that we need to invalidate. Therefore we need
+ * to re-initialize the cache with all pending invalidate bits set.
+ */
+ if (cmd->state.pass) {
+ tu_cache_init(&cmd->state.renderpass_cache);
+ } else {
+ tu_cache_init(&cmd->state.cache);
+ }
}
VkResult
}
}
+static void
+tu_subpass_barrier(struct tu_cmd_buffer *cmd_buffer,
+ const struct tu_subpass_barrier *barrier,
+ bool external)
+{
+ /* Note: we don't know until the end of the subpass whether we'll use
+ * sysmem, so assume sysmem here to be safe.
+ */
+ struct tu_cache_state *cache =
+ external ? &cmd_buffer->state.cache : &cmd_buffer->state.renderpass_cache;
+ enum tu_cmd_access_mask src_flags =
+ vk2tu_access(barrier->src_access_mask, false);
+ enum tu_cmd_access_mask dst_flags =
+ vk2tu_access(barrier->dst_access_mask, false);
+
+ if (barrier->incoherent_ccu_color)
+ src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
+ if (barrier->incoherent_ccu_depth)
+ src_flags |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
+
+ tu_flush_for_access(cache, src_flags, dst_flags);
+}
+
void
tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
const VkRenderPassBeginInfo *pRenderPassBegin,
tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
tu_cmd_prepare_tile_store_ib(cmd);
+ /* Note: because this is external, any flushes will happen before draw_cs
+ * gets called. However deferred flushes could have to happen later as part
+ * of the subpass.
+ */
+ tu_subpass_barrier(cmd, &pass->subpasses[0].start_barrier, true);
+ cmd->state.renderpass_cache.pending_flush_bits =
+ cmd->state.cache.pending_flush_bits;
+ cmd->state.renderpass_cache.flush_bits = 0;
+
tu_emit_load_clear(cmd, pRenderPassBegin);
tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
- tu6_emit_msaa(cmd, cmd->state.subpass, &cmd->draw_cs);
+ tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples);
tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
/* note: use_hw_binning only checks tiling config */
tu_bo_list_add(&cmd->bo_list, iview->image->bo,
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
}
+
+ /* Flag input attachment descriptors for re-emission if necessary */
+ cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
}
void
struct tu_cs *cs = &cmd->draw_cs;
const struct tu_subpass *subpass = cmd->state.subpass++;
- /* TODO:
- * if msaa samples change between subpasses,
- * attachment store is broken for some attachments
- */
+
+ tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
+
if (subpass->resolve_attachments) {
tu6_emit_blit_scissor(cmd, cs, true);
+
for (unsigned i = 0; i < subpass->color_count; i++) {
uint32_t a = subpass->resolve_attachments[i].attachment;
- if (a != VK_ATTACHMENT_UNUSED) {
- tu6_emit_resolve(cmd, cs, a,
- subpass->color_attachments[i].attachment);
- }
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ tu_store_gmem_attachment(cmd, cs, a,
+ subpass->color_attachments[i].attachment);
+
+ if (pass->attachments[a].gmem_offset < 0)
+ continue;
+
+ /* TODO:
+ * check if the resolved attachment is needed by later subpasses,
+ * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
+ */
+ tu_finishme("missing GMEM->GMEM resolve path\n");
+ tu_load_gmem_attachment(cmd, cs, a, true);
}
}
- /* invalidate because reading input attachments will cache GMEM and
- * the cache isn''t updated when GMEM is written
- * TODO: is there a no-cache bit for textures?
- */
- if (cmd->state.subpass->input_count)
- tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE, false);
+ tu_cond_exec_end(cs);
+
+ tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
+
+ tu6_emit_sysmem_resolves(cmd, cs, subpass);
+
+ tu_cond_exec_end(cs);
+
+ /* Handle dependencies for the next subpass */
+ tu_subpass_barrier(cmd, &cmd->state.subpass->start_barrier, false);
/* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
tu6_emit_zs(cmd, cmd->state.subpass, cs);
tu6_emit_mrt(cmd, cmd->state.subpass, cs);
- tu6_emit_msaa(cmd, cmd->state.subpass, cs);
+ tu6_emit_msaa(cs, cmd->state.subpass->samples);
tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
- /* Emit flushes so that input attachments will read the correct value. This
- * is for sysmem only, although it shouldn't do much harm on gmem.
- */
- tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
- tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
-
- /* TODO:
- * since we don't know how to do GMEM->GMEM resolve,
- * resolve attachments are resolved to memory then loaded to GMEM again if needed
- */
- if (subpass->resolve_attachments) {
- for (unsigned i = 0; i < subpass->color_count; i++) {
- uint32_t a = subpass->resolve_attachments[i].attachment;
- if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
- tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
- tu6_emit_predicated_blit(cmd, cs, a, a, false);
- }
- }
- }
+ /* Flag input attachment descriptors for re-emission if necessary */
+ cmd->state.dirty |= TU_CMD_DIRTY_INPUT_ATTACHMENTS;
}
void
#define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
#define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
+#define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
enum tu_draw_state_group_id
{
TU_DRAW_STATE_PROGRAM,
TU_DRAW_STATE_PROGRAM_BINNING,
+ TU_DRAW_STATE_VB,
TU_DRAW_STATE_VI,
TU_DRAW_STATE_VI_BINNING,
TU_DRAW_STATE_VP,
TU_DRAW_STATE_DS,
TU_DRAW_STATE_BLEND,
TU_DRAW_STATE_VS_CONST,
+ TU_DRAW_STATE_GS_CONST,
TU_DRAW_STATE_FS_CONST,
- TU_DRAW_STATE_VS_TEX,
- TU_DRAW_STATE_FS_TEX_SYSMEM,
- TU_DRAW_STATE_FS_TEX_GMEM,
- TU_DRAW_STATE_FS_IBO,
+ TU_DRAW_STATE_DESC_SETS,
+ TU_DRAW_STATE_DESC_SETS_GMEM,
+ TU_DRAW_STATE_DESC_SETS_LOAD,
TU_DRAW_STATE_VS_PARAMS,
TU_DRAW_STATE_COUNT,
struct tu_cs_entry ib;
};
-const static void *
-sampler_ptr(struct tu_descriptor_state *descriptors_state,
- const struct tu_descriptor_map *map, unsigned i,
- unsigned array_index)
-{
- assert(descriptors_state->valid & (1 << map->set[i]));
-
- struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
- assert(map->binding[i] < set->layout->binding_count);
-
- const struct tu_descriptor_set_binding_layout *layout =
- &set->layout->binding[map->binding[i]];
-
- if (layout->immutable_samplers_offset) {
- const uint32_t *immutable_samplers =
- tu_immutable_samplers(set->layout, layout);
-
- return &immutable_samplers[array_index * A6XX_TEX_SAMP_DWORDS];
- }
-
- switch (layout->type) {
- case VK_DESCRIPTOR_TYPE_SAMPLER:
- return &set->mapped_ptr[layout->offset / 4];
- case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
- return &set->mapped_ptr[layout->offset / 4 + A6XX_TEX_CONST_DWORDS +
- array_index * (A6XX_TEX_CONST_DWORDS + A6XX_TEX_SAMP_DWORDS)];
- default:
- unreachable("unimplemented descriptor type");
- break;
- }
-}
-
-static void
-write_tex_const(struct tu_cmd_buffer *cmd,
- uint32_t *dst,
- struct tu_descriptor_state *descriptors_state,
- const struct tu_descriptor_map *map,
- unsigned i, unsigned array_index, bool is_sysmem)
-{
- assert(descriptors_state->valid & (1 << map->set[i]));
-
- struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
- assert(map->binding[i] < set->layout->binding_count);
-
- const struct tu_descriptor_set_binding_layout *layout =
- &set->layout->binding[map->binding[i]];
-
- switch (layout->type) {
- case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
- case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
- case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
- case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
- memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
- array_index * A6XX_TEX_CONST_DWORDS],
- A6XX_TEX_CONST_DWORDS * 4);
- break;
- case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
- memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
- array_index *
- (A6XX_TEX_CONST_DWORDS +
- A6XX_TEX_SAMP_DWORDS)],
- A6XX_TEX_CONST_DWORDS * 4);
- break;
- default:
- unreachable("unimplemented descriptor type");
- break;
- }
-
- if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT && !is_sysmem) {
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
- uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
- array_index].attachment;
- const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
-
- assert(att->gmem_offset >= 0);
-
- dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
- dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
- dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
- dst[2] |=
- A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
- A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
- dst[3] = 0;
- dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
- dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
- for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
- dst[i] = 0;
-
- if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
- tu_finishme("patch input attachment pitch for secondary cmd buffer");
- }
-}
-
-static void
-write_image_ibo(struct tu_cmd_buffer *cmd,
- uint32_t *dst,
- struct tu_descriptor_state *descriptors_state,
- const struct tu_descriptor_map *map,
- unsigned i, unsigned array_index)
-{
- assert(descriptors_state->valid & (1 << map->set[i]));
-
- struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
- assert(map->binding[i] < set->layout->binding_count);
-
- const struct tu_descriptor_set_binding_layout *layout =
- &set->layout->binding[map->binding[i]];
-
- assert(layout->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE);
-
- memcpy(dst, &set->mapped_ptr[layout->offset / 4 +
- (array_index * 2 + 1) * A6XX_TEX_CONST_DWORDS],
- A6XX_TEX_CONST_DWORDS * 4);
-}
-
-static uint64_t
-buffer_ptr(struct tu_descriptor_state *descriptors_state,
- const struct tu_descriptor_map *map,
- unsigned i, unsigned array_index)
-{
- assert(descriptors_state->valid & (1 << map->set[i]));
-
- struct tu_descriptor_set *set = descriptors_state->sets[map->set[i]];
- assert(map->binding[i] < set->layout->binding_count);
-
- const struct tu_descriptor_set_binding_layout *layout =
- &set->layout->binding[map->binding[i]];
-
- switch (layout->type) {
- case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
- case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
- return descriptors_state->dynamic_buffers[layout->dynamic_offset_offset +
- array_index];
- case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
- case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
- return (uint64_t) set->mapped_ptr[layout->offset / 4 + array_index * 2 + 1] << 32 |
- set->mapped_ptr[layout->offset / 4 + array_index * 2];
- default:
- unreachable("unimplemented descriptor type");
- break;
- }
-}
-
-static inline uint32_t
-tu6_stage2opcode(gl_shader_stage type)
-{
- switch (type) {
- case MESA_SHADER_VERTEX:
- case MESA_SHADER_TESS_CTRL:
- case MESA_SHADER_TESS_EVAL:
- case MESA_SHADER_GEOMETRY:
- return CP_LOAD_STATE6_GEOM;
- case MESA_SHADER_FRAGMENT:
- case MESA_SHADER_COMPUTE:
- case MESA_SHADER_KERNEL:
- return CP_LOAD_STATE6_FRAG;
- default:
- unreachable("bad shader type");
- }
-}
-
-static inline enum a6xx_state_block
-tu6_stage2shadersb(gl_shader_stage type)
-{
- switch (type) {
- case MESA_SHADER_VERTEX:
- return SB6_VS_SHADER;
- case MESA_SHADER_FRAGMENT:
- return SB6_FS_SHADER;
- case MESA_SHADER_COMPUTE:
- case MESA_SHADER_KERNEL:
- return SB6_CS_SHADER;
- default:
- unreachable("bad shader type");
- return ~0;
- }
-}
-
static void
tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
struct tu_descriptor_state *descriptors_state,
&pipeline->program.link[type];
const struct ir3_ubo_analysis_state *state = &link->ubo_state;
- for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
- if (state->range[i].start < state->range[i].end) {
- uint32_t size = state->range[i].end - state->range[i].start;
- uint32_t offset = state->range[i].start;
-
- /* and even if the start of the const buffer is before
- * first_immediate, the end may not be:
- */
- size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
-
- if (size == 0)
- continue;
-
- /* things should be aligned to vec4: */
- debug_assert((state->range[i].offset % 16) == 0);
- debug_assert((size % 16) == 0);
- debug_assert((offset % 16) == 0);
-
- if (i == 0) {
- /* push constants */
- tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
- tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
- CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
- CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
- CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
- CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
- tu_cs_emit(cs, 0);
- tu_cs_emit(cs, 0);
- for (unsigned i = 0; i < size / 4; i++)
- tu_cs_emit(cs, push_constants[i + offset / 4]);
- continue;
- }
-
- /* Look through the UBO map to find our UBO index, and get the VA for
- * that UBO.
- */
- uint64_t va = 0;
- uint32_t ubo_idx = i - 1;
- uint32_t ubo_map_base = 0;
- for (int j = 0; j < link->ubo_map.num; j++) {
- if (ubo_idx >= ubo_map_base &&
- ubo_idx < ubo_map_base + link->ubo_map.array_size[j]) {
- va = buffer_ptr(descriptors_state, &link->ubo_map, j,
- ubo_idx - ubo_map_base);
- break;
- }
- ubo_map_base += link->ubo_map.array_size[j];
- }
- assert(va);
-
- tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
- tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
- CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
- CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
- CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
- CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
- tu_cs_emit_qw(cs, va + offset);
- }
+ if (link->push_consts.count > 0) {
+ unsigned num_units = link->push_consts.count;
+ unsigned offset = link->push_consts.lo;
+ tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units * 4);
+ tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
+ CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
+ CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
+ CP_LOAD_STATE6_0_NUM_UNIT(num_units));
+ tu_cs_emit(cs, 0);
+ tu_cs_emit(cs, 0);
+ for (unsigned i = 0; i < num_units * 4; i++)
+ tu_cs_emit(cs, push_constants[i + offset * 4]);
}
-}
-static void
-tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
- struct tu_descriptor_state *descriptors_state,
- gl_shader_stage type)
-{
- const struct tu_program_descriptor_linkage *link =
- &pipeline->program.link[type];
+ for (uint32_t i = 0; i < state->num_enabled; i++) {
+ uint32_t size = state->range[i].end - state->range[i].start;
+ uint32_t offset = state->range[i].start;
- uint32_t num = MIN2(link->ubo_map.num_desc, link->const_state.num_ubos);
- uint32_t anum = align(num, 2);
+ /* and even if the start of the const buffer is before
+ * first_immediate, the end may not be:
+ */
+ size = MIN2(size, (16 * link->constlen) - state->range[i].offset);
- if (!num)
- return;
+ if (size == 0)
+ continue;
- tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (2 * anum));
- tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(link->const_state.offsets.ubo) |
- CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
- CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
- CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
- CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
- tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
- tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
-
- unsigned emitted = 0;
- for (unsigned i = 0; emitted < num && i < link->ubo_map.num; i++) {
- for (unsigned j = 0; emitted < num && j < link->ubo_map.array_size[i]; j++) {
- tu_cs_emit_qw(cs, buffer_ptr(descriptors_state, &link->ubo_map, i, j));
- emitted++;
- }
- }
+ /* things should be aligned to vec4: */
+ debug_assert((state->range[i].offset % 16) == 0);
+ debug_assert((size % 16) == 0);
+ debug_assert((offset % 16) == 0);
- for (; emitted < anum; emitted++) {
- tu_cs_emit(cs, 0xffffffff);
- tu_cs_emit(cs, 0xffffffff);
+ /* Dig out the descriptor from the descriptor state and read the VA from
+ * it.
+ */
+ assert(state->range[i].bindless);
+ uint32_t *base = state->range[i].bindless_base == MAX_SETS ?
+ descriptors_state->dynamic_descriptors :
+ descriptors_state->sets[state->range[i].bindless_base]->mapped_ptr;
+ unsigned block = state->range[i].block;
+ /* If the block in the shader here is in the dynamic descriptor set, it
+ * is an index into the dynamic descriptor set which is combined from
+ * dynamic descriptors and input attachments on-the-fly, and we don't
+ * have access to it here. Instead we work backwards to get the index
+ * into dynamic_descriptors.
+ */
+ if (state->range[i].bindless_base == MAX_SETS)
+ block -= pipeline->layout->input_attachment_count;
+ uint32_t *desc = base + block * A6XX_TEX_CONST_DWORDS;
+ uint64_t va = desc[0] | ((uint64_t)(desc[1] & A6XX_UBO_1_BASE_HI__MASK) << 32);
+ assert(va);
+
+ tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
+ tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
+ CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
+ CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
+ CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
+ tu_cs_emit_qw(cs, va + offset);
}
}
tu_cs_begin_sub_stream(&cmd->sub_cs, 512, &cs); /* TODO: maximum size? */
tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
- tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
}
return VK_SUCCESS;
}
-static VkResult
-tu6_emit_textures(struct tu_cmd_buffer *cmd,
- const struct tu_pipeline *pipeline,
- struct tu_descriptor_state *descriptors_state,
- gl_shader_stage type,
- struct tu_cs_entry *entry,
- bool is_sysmem)
+static struct tu_cs_entry
+tu6_emit_vertex_buffers(struct tu_cmd_buffer *cmd,
+ const struct tu_pipeline *pipeline)
{
- struct tu_cs *draw_state = &cmd->sub_cs;
- const struct tu_program_descriptor_linkage *link =
- &pipeline->program.link[type];
- VkResult result;
-
- if (link->texture_map.num_desc == 0 && link->sampler_map.num_desc == 0) {
- *entry = (struct tu_cs_entry) {};
- return VK_SUCCESS;
- }
-
- /* allocate and fill texture state */
- struct ts_cs_memory tex_const;
- result = tu_cs_alloc(draw_state, link->texture_map.num_desc,
- A6XX_TEX_CONST_DWORDS, &tex_const);
- if (result != VK_SUCCESS)
- return result;
-
- int tex_index = 0;
- for (unsigned i = 0; i < link->texture_map.num; i++) {
- for (int j = 0; j < link->texture_map.array_size[i]; j++) {
- write_tex_const(cmd,
- &tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
- descriptors_state, &link->texture_map, i, j,
- is_sysmem);
- }
- }
-
- /* allocate and fill sampler state */
- struct ts_cs_memory tex_samp = { 0 };
- if (link->sampler_map.num_desc) {
- result = tu_cs_alloc(draw_state, link->sampler_map.num_desc,
- A6XX_TEX_SAMP_DWORDS, &tex_samp);
- if (result != VK_SUCCESS)
- return result;
-
- int sampler_index = 0;
- for (unsigned i = 0; i < link->sampler_map.num; i++) {
- for (int j = 0; j < link->sampler_map.array_size[i]; j++) {
- const uint32_t *sampler = sampler_ptr(descriptors_state,
- &link->sampler_map,
- i, j);
- memcpy(&tex_samp.map[A6XX_TEX_SAMP_DWORDS * sampler_index++],
- sampler, A6XX_TEX_SAMP_DWORDS * 4);
- }
- }
- }
-
- unsigned tex_samp_reg, tex_const_reg, tex_count_reg;
- enum a6xx_state_block sb;
-
- switch (type) {
- case MESA_SHADER_VERTEX:
- sb = SB6_VS_TEX;
- tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
- tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
- break;
- case MESA_SHADER_FRAGMENT:
- sb = SB6_FS_TEX;
- tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
- tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
- break;
- case MESA_SHADER_COMPUTE:
- sb = SB6_CS_TEX;
- tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
- tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
- break;
- default:
- unreachable("bad state block");
- }
-
struct tu_cs cs;
- result = tu_cs_begin_sub_stream(draw_state, 16, &cs);
- if (result != VK_SUCCESS)
- return result;
+ tu_cs_begin_sub_stream(&cmd->sub_cs, 4 * MAX_VBS, &cs);
- if (link->sampler_map.num_desc) {
- /* output sampler state: */
- tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
- tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
- CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
- CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
- CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
- CP_LOAD_STATE6_0_NUM_UNIT(link->sampler_map.num_desc));
- tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
-
- tu_cs_emit_pkt4(&cs, tex_samp_reg, 2);
- tu_cs_emit_qw(&cs, tex_samp.iova); /* SRC_ADDR_LO/HI */
- }
+ int binding;
+ for_each_bit(binding, pipeline->vi.bindings_used) {
+ const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
+ const VkDeviceSize offset = buf->bo_offset +
+ cmd->state.vb.offsets[binding];
- /* emit texture state: */
- tu_cs_emit_pkt7(&cs, tu6_stage2opcode(type), 3);
- tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
- CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
- CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
- CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
- CP_LOAD_STATE6_0_NUM_UNIT(link->texture_map.num_desc));
- tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
+ tu_cs_emit_regs(&cs,
+ A6XX_VFD_FETCH_BASE(binding, .bo = buf->bo, .bo_offset = offset),
+ A6XX_VFD_FETCH_SIZE(binding, buf->size - offset));
- tu_cs_emit_pkt4(&cs, tex_const_reg, 2);
- tu_cs_emit_qw(&cs, tex_const.iova); /* SRC_ADDR_LO/HI */
+ }
- tu_cs_emit_pkt4(&cs, tex_count_reg, 1);
- tu_cs_emit(&cs, link->texture_map.num_desc);
+ cmd->vertex_bindings_set = pipeline->vi.bindings_used;
- *entry = tu_cs_end_sub_stream(draw_state, &cs);
- return VK_SUCCESS;
+ return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
}
static VkResult
-tu6_emit_ibo(struct tu_cmd_buffer *cmd,
- const struct tu_pipeline *pipeline,
- struct tu_descriptor_state *descriptors_state,
- gl_shader_stage type,
- struct tu_cs_entry *entry)
+tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
+ const struct tu_pipeline *pipeline,
+ VkPipelineBindPoint bind_point,
+ struct tu_cs_entry *entry,
+ bool gmem)
{
struct tu_cs *draw_state = &cmd->sub_cs;
- const struct tu_program_descriptor_linkage *link =
- &pipeline->program.link[type];
+ struct tu_pipeline_layout *layout = pipeline->layout;
+ struct tu_descriptor_state *descriptors_state =
+ tu_get_descriptors_state(cmd, bind_point);
+ const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
+ const uint32_t *input_attachment_idx =
+ pipeline->program.input_attachment_idx;
+ uint32_t num_dynamic_descs = layout->dynamic_offset_count +
+ layout->input_attachment_count;
+ struct ts_cs_memory dynamic_desc_set;
VkResult result;
- unsigned num_desc = link->ssbo_map.num_desc + link->image_map.num_desc;
-
- if (num_desc == 0) {
- *entry = (struct tu_cs_entry) {};
- return VK_SUCCESS;
- }
-
- struct ts_cs_memory ibo_const;
- result = tu_cs_alloc(draw_state, num_desc,
- A6XX_TEX_CONST_DWORDS, &ibo_const);
- if (result != VK_SUCCESS)
- return result;
+ if (num_dynamic_descs > 0) {
+ /* allocate and fill out dynamic descriptor set */
+ result = tu_cs_alloc(draw_state, num_dynamic_descs,
+ A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
+ if (result != VK_SUCCESS)
+ return result;
- int ssbo_index = 0;
- for (unsigned i = 0; i < link->ssbo_map.num; i++) {
- for (int j = 0; j < link->ssbo_map.array_size[i]; j++) {
- uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
-
- uint64_t va = buffer_ptr(descriptors_state, &link->ssbo_map, i, j);
- /* We don't expose robustBufferAccess, so leave the size unlimited. */
- uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
-
- dst[0] = A6XX_IBO_0_FMT(FMT6_32_UINT);
- dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
- A6XX_IBO_1_HEIGHT(sz >> 15);
- dst[2] = A6XX_IBO_2_UNK4 |
- A6XX_IBO_2_UNK31 |
- A6XX_IBO_2_TYPE(A6XX_TEX_1D);
- dst[3] = 0;
- dst[4] = va;
- dst[5] = va >> 32;
- for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
- dst[i] = 0;
-
- ssbo_index++;
+ memcpy(dynamic_desc_set.map, descriptors_state->input_attachments,
+ layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
+
+ if (gmem) {
+ /* Patch input attachments to refer to GMEM instead */
+ for (unsigned i = 0; i < layout->input_attachment_count; i++) {
+ uint32_t *dst =
+ &dynamic_desc_set.map[A6XX_TEX_CONST_DWORDS * i];
+
+ /* The compiler has already laid out input_attachment_idx in the
+ * final order of input attachments, so there's no need to go
+ * through the pipeline layout finding input attachments.
+ */
+ unsigned attachment_idx = input_attachment_idx[i];
+
+ /* It's possible for the pipeline layout to include an input
+ * attachment which doesn't actually exist for the current
+ * subpass. Of course, this is only valid so long as the pipeline
+ * doesn't try to actually load that attachment. Just skip
+ * patching in that scenario to avoid out-of-bounds accesses.
+ */
+ if (attachment_idx >= cmd->state.subpass->input_count)
+ continue;
+
+ uint32_t a = cmd->state.subpass->input_attachments[attachment_idx].attachment;
+ const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
+
+ assert(att->gmem_offset >= 0);
+
+ dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
+ dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
+ dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
+ dst[2] |=
+ A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
+ A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
+ dst[3] = 0;
+ dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
+ dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
+ for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
+ dst[i] = 0;
+
+ if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
+ tu_finishme("patch input attachment pitch for secondary cmd buffer");
+ }
}
- }
- for (unsigned i = 0; i < link->image_map.num; i++) {
- for (int j = 0; j < link->image_map.array_size[i]; j++) {
- uint32_t *dst = &ibo_const.map[A6XX_TEX_CONST_DWORDS * ssbo_index];
+ memcpy(dynamic_desc_set.map + layout->input_attachment_count * A6XX_TEX_CONST_DWORDS,
+ descriptors_state->dynamic_descriptors,
+ layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
+ }
- write_image_ibo(cmd, dst,
- descriptors_state, &link->image_map, i, j);
+ uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg;
+ uint32_t hlsq_update_value;
+ switch (bind_point) {
+ case VK_PIPELINE_BIND_POINT_GRAPHICS:
+ sp_bindless_base_reg = REG_A6XX_SP_BINDLESS_BASE(0);
+ hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
+ hlsq_update_value = 0x7c000;
+ break;
+ case VK_PIPELINE_BIND_POINT_COMPUTE:
+ sp_bindless_base_reg = REG_A6XX_SP_CS_BINDLESS_BASE(0);
+ hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
+ hlsq_update_value = 0x3e00;
+ break;
+ default:
+ unreachable("bad bind point");
+ }
- ssbo_index++;
- }
+ /* Be careful here to *not* refer to the pipeline, so that if only the
+ * pipeline changes we don't have to emit this again (except if there are
+ * dynamic descriptors in the pipeline layout). This means always emitting
+ * all the valid descriptors, which means that we always have to put the
+ * dynamic descriptor in the driver-only slot at the end
+ */
+ uint32_t num_user_sets = util_last_bit(descriptors_state->valid);
+ uint32_t num_sets = num_user_sets;
+ if (num_dynamic_descs > 0) {
+ num_user_sets = MAX_SETS;
+ num_sets = num_user_sets + 1;
}
- assert(ssbo_index == num_desc);
+ unsigned regs[2] = { sp_bindless_base_reg, hlsq_bindless_base_reg };
struct tu_cs cs;
- result = tu_cs_begin_sub_stream(draw_state, 7, &cs);
+ result = tu_cs_begin_sub_stream(draw_state, ARRAY_SIZE(regs) * (1 + num_sets * 2) + 2, &cs);
if (result != VK_SUCCESS)
return result;
- uint32_t opcode, ibo_addr_reg;
- enum a6xx_state_block sb;
- enum a6xx_state_type st;
+ if (num_sets > 0) {
+ for (unsigned i = 0; i < ARRAY_SIZE(regs); i++) {
+ tu_cs_emit_pkt4(&cs, regs[i], num_sets * 2);
+ for (unsigned j = 0; j < num_user_sets; j++) {
+ if (descriptors_state->valid & (1 << j)) {
+ /* magic | 3 copied from the blob */
+ tu_cs_emit_qw(&cs, descriptors_state->sets[j]->va | 3);
+ } else {
+ tu_cs_emit_qw(&cs, 0 | 3);
+ }
+ }
+ if (num_dynamic_descs > 0) {
+ tu_cs_emit_qw(&cs, dynamic_desc_set.iova | 3);
+ }
+ }
- switch (type) {
- case MESA_SHADER_FRAGMENT:
- opcode = CP_LOAD_STATE6;
- st = ST6_SHADER;
- sb = SB6_IBO;
- ibo_addr_reg = REG_A6XX_SP_IBO_LO;
- break;
- case MESA_SHADER_COMPUTE:
- opcode = CP_LOAD_STATE6_FRAG;
- st = ST6_IBO;
- sb = SB6_CS_SHADER;
- ibo_addr_reg = REG_A6XX_SP_CS_IBO_LO;
- break;
- default:
- unreachable("unsupported stage for ibos");
+ tu_cs_emit_regs(&cs, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value));
}
- /* emit texture state: */
- tu_cs_emit_pkt7(&cs, opcode, 3);
- tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
- CP_LOAD_STATE6_0_STATE_TYPE(st) |
- CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
- CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
- CP_LOAD_STATE6_0_NUM_UNIT(num_desc));
- tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
-
- tu_cs_emit_pkt4(&cs, ibo_addr_reg, 2);
- tu_cs_emit_qw(&cs, ibo_const.iova); /* SRC_ADDR_LO/HI */
-
*entry = tu_cs_end_sub_stream(draw_state, &cs);
return VK_SUCCESS;
}
tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_SIZE(i, buf->size));
if (cmd->state.streamout_reset & (1 << i)) {
- offset *= tf->stride[i];
-
tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, offset));
cmd->state.streamout_reset &= ~(1 << i);
} else {
dynamic->stencil_reference.back);
}
- if (cmd->state.dirty &
- (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_VERTEX_BUFFERS)) {
- for (uint32_t i = 0; i < pipeline->vi.count; i++) {
- const uint32_t binding = pipeline->vi.bindings[i];
- const struct tu_buffer *buf = cmd->state.vb.buffers[binding];
- const VkDeviceSize offset = buf->bo_offset +
- cmd->state.vb.offsets[binding];
- const VkDeviceSize size =
- offset < buf->size ? buf->size - offset : 0;
-
- tu_cs_emit_regs(cs,
- A6XX_VFD_FETCH_BASE(i, .bo = buf->bo, .bo_offset = offset),
- A6XX_VFD_FETCH_SIZE(i, size));
- }
+ if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
+ (pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
+ tu6_emit_viewport(cs, &cmd->state.dynamic.viewport.viewports[0]);
+ }
+
+ if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_SCISSOR) &&
+ (pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
+ tu6_emit_scissor(cs, &cmd->state.dynamic.scissor.scissors[0]);
}
if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
.enable_mask = ENABLE_ALL,
.ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
};
+ draw_state_groups[draw_state_group_count++] =
+ (struct tu_draw_state_group) {
+ .id = TU_DRAW_STATE_GS_CONST,
+ .enable_mask = ENABLE_ALL,
+ .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_GEOMETRY)
+ };
draw_state_groups[draw_state_group_count++] =
(struct tu_draw_state_group) {
.id = TU_DRAW_STATE_FS_CONST,
};
}
+ if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
+ draw_state_groups[draw_state_group_count++] =
+ (struct tu_draw_state_group) {
+ .id = TU_DRAW_STATE_VB,
+ .enable_mask = ENABLE_ALL,
+ .ib = tu6_emit_vertex_buffers(cmd, pipeline)
+ };
+ }
+
if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS)
tu6_emit_streamout(cmd, cs);
- if (cmd->state.dirty &
- (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
- struct tu_cs_entry vs_tex, fs_tex_sysmem, fs_tex_gmem, fs_ibo;
-
- result = tu6_emit_textures(cmd, pipeline, descriptors_state,
- MESA_SHADER_VERTEX, &vs_tex, false);
- if (result != VK_SUCCESS)
- return result;
-
- /* TODO: we could emit just one texture descriptor draw state when there
- * are no input attachments, which is the most common case. We could
- * also split out the sampler state, which doesn't change even for input
- * attachments.
- */
- result = tu6_emit_textures(cmd, pipeline, descriptors_state,
- MESA_SHADER_FRAGMENT, &fs_tex_sysmem, true);
- if (result != VK_SUCCESS)
- return result;
-
- result = tu6_emit_textures(cmd, pipeline, descriptors_state,
- MESA_SHADER_FRAGMENT, &fs_tex_gmem, false);
- if (result != VK_SUCCESS)
- return result;
-
- result = tu6_emit_ibo(cmd, pipeline, descriptors_state,
- MESA_SHADER_FRAGMENT, &fs_ibo);
+ /* If there are any any dynamic descriptors, then we may need to re-emit
+ * them after every pipeline change in case the number of input attachments
+ * changes. We also always need to re-emit after a pipeline change if there
+ * are any input attachments, because the input attachment index comes from
+ * the pipeline. Finally, it can also happen that the subpass changes
+ * without the pipeline changing, in which case the GMEM descriptors need
+ * to be patched differently.
+ *
+ * TODO: We could probably be clever and avoid re-emitting state on
+ * pipeline changes if the number of input attachments is always 0. We
+ * could also only re-emit dynamic state.
+ */
+ if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS ||
+ ((pipeline->layout->dynamic_offset_count +
+ pipeline->layout->input_attachment_count > 0) &&
+ cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) ||
+ (pipeline->layout->input_attachment_count > 0 &&
+ cmd->state.dirty & TU_CMD_DIRTY_INPUT_ATTACHMENTS)) {
+ struct tu_cs_entry desc_sets, desc_sets_gmem;
+ bool need_gmem_desc_set = pipeline->layout->input_attachment_count > 0;
+
+ result = tu6_emit_descriptor_sets(cmd, pipeline,
+ VK_PIPELINE_BIND_POINT_GRAPHICS,
+ &desc_sets, false);
if (result != VK_SUCCESS)
return result;
draw_state_groups[draw_state_group_count++] =
(struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_VS_TEX,
- .enable_mask = ENABLE_ALL,
- .ib = vs_tex,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_FS_TEX_GMEM,
- .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
- .ib = fs_tex_gmem,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_FS_TEX_SYSMEM,
- .enable_mask = CP_SET_DRAW_STATE__0_SYSMEM,
- .ib = fs_tex_sysmem,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_FS_IBO,
- .enable_mask = ENABLE_DRAW,
- .ib = fs_ibo,
+ .id = TU_DRAW_STATE_DESC_SETS,
+ .enable_mask = need_gmem_desc_set ? ENABLE_NON_GMEM : ENABLE_ALL,
+ .ib = desc_sets,
};
+
+ if (need_gmem_desc_set) {
+ result = tu6_emit_descriptor_sets(cmd, pipeline,
+ VK_PIPELINE_BIND_POINT_GRAPHICS,
+ &desc_sets_gmem, true);
+ if (result != VK_SUCCESS)
+ return result;
+
+ draw_state_groups[draw_state_group_count++] =
+ (struct tu_draw_state_group) {
+ .id = TU_DRAW_STATE_DESC_SETS_GMEM,
+ .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
+ .ib = desc_sets_gmem,
+ };
+ }
+
+ /* We need to reload the descriptors every time the descriptor sets
+ * change. However, the commands we send only depend on the pipeline
+ * because the whole point is to cache descriptors which are used by the
+ * pipeline. There's a problem here, in that the firmware has an
+ * "optimization" which skips executing groups that are set to the same
+ * value as the last draw. This means that if the descriptor sets change
+ * but not the pipeline, we'd try to re-execute the same buffer which
+ * the firmware would ignore and we wouldn't pre-load the new
+ * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
+ * the descriptor sets change, which we emulate here by copying the
+ * pre-prepared buffer.
+ */
+ const struct tu_cs_entry *load_entry = &pipeline->load_state.state_ib;
+ if (load_entry->size > 0) {
+ struct tu_cs load_cs;
+ result = tu_cs_begin_sub_stream(&cmd->sub_cs, load_entry->size, &load_cs);
+ if (result != VK_SUCCESS)
+ return result;
+ tu_cs_emit_array(&load_cs,
+ (uint32_t *)((char *)load_entry->bo->map + load_entry->offset),
+ load_entry->size / 4);
+ struct tu_cs_entry load_copy = tu_cs_end_sub_stream(&cmd->sub_cs, &load_cs);
+
+ draw_state_groups[draw_state_group_count++] =
+ (struct tu_draw_state_group) {
+ .id = TU_DRAW_STATE_DESC_SETS_LOAD,
+ /* The blob seems to not enable this for binning, even when
+ * resources would actually be used in the binning shader.
+ * Presumably the overhead of prefetching the resources isn't
+ * worth it.
+ */
+ .enable_mask = ENABLE_DRAW,
+ .ib = load_copy,
+ };
+ }
}
struct tu_cs_entry vs_params;
tu_cs_sanity_check(cs);
/* track BOs */
- if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
- for (uint32_t i = 0; i < MAX_VBS; i++) {
- const struct tu_buffer *buf = cmd->state.vb.buffers[i];
- if (buf)
- tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
- }
- }
if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
unsigned i;
for_each_bit(i, descriptors_state->valid) {
struct tu_descriptor_set *set = descriptors_state->sets[i];
- for (unsigned j = 0; j < set->layout->buffer_count; ++j)
- if (set->descriptors[j]) {
- tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
+ for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
+ if (set->buffers[j]) {
+ tu_bo_list_add(&cmd->bo_list, set->buffers[j],
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
}
+ }
+ if (set->size > 0) {
+ tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
+ MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
+ }
}
}
if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS) {
}
}
+ /* There are too many graphics dirty bits to list here, so just list the
+ * bits to preserve instead. The only things not emitted here are
+ * compute-related state.
+ */
+ cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
+
/* Fragment shader state overwrites compute shader state, so flag the
* compute pipeline for re-emit.
*/
- cmd->state.dirty = TU_CMD_DIRTY_COMPUTE_PIPELINE;
+ cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
return VK_SUCCESS;
}
struct tu_cs *cs = &cmd->draw_cs;
VkResult result;
+ tu_emit_cache_flush_renderpass(cmd, cs);
+
result = tu6_bind_draw_states(cmd, cs, draw);
if (result != VK_SUCCESS) {
cmd->record_result = result;
if (cmd->state.streamout_enabled) {
for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
if (cmd->state.streamout_enabled & (1 << i))
- tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i, false);
+ tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i);
}
}
- cmd->wait_for_idle = true;
-
tu_cs_sanity_check(cs);
}
&cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
VkResult result;
+ /* TODO: We could probably flush less if we add a compute_flush_bits
+ * bitfield.
+ */
+ tu_emit_cache_flush(cmd, cs);
+
if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
tu_cs_emit_ib(cs, &pipeline->program.state_ib);
tu_emit_compute_driver_params(cs, pipeline, info);
- result = tu6_emit_textures(cmd, pipeline, descriptors_state,
- MESA_SHADER_COMPUTE, &ib, false);
- if (result != VK_SUCCESS) {
- cmd->record_result = result;
- return;
- }
-
- if (ib.size)
- tu_cs_emit_ib(cs, &ib);
-
- result = tu6_emit_ibo(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE, &ib);
- if (result != VK_SUCCESS) {
- cmd->record_result = result;
- return;
- }
-
- if (ib.size)
- tu_cs_emit_ib(cs, &ib);
+ if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS) {
+ result = tu6_emit_descriptor_sets(cmd, pipeline,
+ VK_PIPELINE_BIND_POINT_COMPUTE, &ib,
+ false);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
- /* track BOs */
- if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
+ /* track BOs */
unsigned i;
for_each_bit(i, descriptors_state->valid) {
struct tu_descriptor_set *set = descriptors_state->sets[i];
- for (unsigned j = 0; j < set->layout->buffer_count; ++j)
- if (set->descriptors[j]) {
- tu_bo_list_add(&cmd->bo_list, set->descriptors[j],
+ for (unsigned j = 0; j < set->layout->buffer_count; ++j) {
+ if (set->buffers[j]) {
+ tu_bo_list_add(&cmd->bo_list, set->buffers[j],
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
}
+ }
+
+ if (set->size > 0) {
+ tu_bo_list_add(&cmd->bo_list, &set->pool->bo,
+ MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
+ }
}
}
+ if (ib.size)
+ tu_cs_emit_ib(cs, &ib);
+
+ if ((cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS) &&
+ pipeline->load_state.state_ib.size > 0) {
+ tu_cs_emit_ib(cs, &pipeline->load_state.state_ib);
+ }
+
+ cmd->state.dirty &=
+ ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS | TU_CMD_DIRTY_COMPUTE_PIPELINE);
+
/* Compute shader state overwrites fragment shader state, so we flag the
* graphics pipeline for re-emit.
*/
- cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
+ cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE;
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
}
tu_cs_emit_wfi(cs);
-
- tu6_emit_cache_flush(cmd, cs);
}
void
tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
+ cmd_buffer->state.cache.pending_flush_bits |=
+ cmd_buffer->state.renderpass_cache.pending_flush_bits;
+ tu_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier, true);
+
cmd_buffer->state.pass = NULL;
cmd_buffer->state.subpass = NULL;
cmd_buffer->state.framebuffer = NULL;
};
static void
-tu_barrier(struct tu_cmd_buffer *cmd_buffer,
+tu_barrier(struct tu_cmd_buffer *cmd,
uint32_t memoryBarrierCount,
const VkMemoryBarrier *pMemoryBarriers,
uint32_t bufferMemoryBarrierCount,
const VkImageMemoryBarrier *pImageMemoryBarriers,
const struct tu_barrier_info *info)
{
+ struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
+ VkAccessFlags srcAccessMask = 0;
+ VkAccessFlags dstAccessMask = 0;
+
+ for (uint32_t i = 0; i < memoryBarrierCount; i++) {
+ srcAccessMask |= pMemoryBarriers[i].srcAccessMask;
+ dstAccessMask |= pMemoryBarriers[i].dstAccessMask;
+ }
+
+ for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
+ srcAccessMask |= pBufferMemoryBarriers[i].srcAccessMask;
+ dstAccessMask |= pBufferMemoryBarriers[i].dstAccessMask;
+ }
+
+ enum tu_cmd_access_mask src_flags = 0;
+ enum tu_cmd_access_mask dst_flags = 0;
+
+ for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
+ TU_FROM_HANDLE(tu_image, image, pImageMemoryBarriers[i].image);
+ VkImageLayout old_layout = pImageMemoryBarriers[i].oldLayout;
+ /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
+ if (old_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
+ (image->tiling != VK_IMAGE_TILING_LINEAR &&
+ old_layout == VK_IMAGE_LAYOUT_PREINITIALIZED)) {
+ /* The underlying memory for this image may have been used earlier
+ * within the same queue submission for a different image, which
+ * means that there may be old, stale cache entries which are in the
+ * "wrong" location, which could cause problems later after writing
+ * to the image. We don't want these entries being flushed later and
+ * overwriting the actual image, so we need to flush the CCU.
+ */
+ src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
+ }
+ srcAccessMask |= pImageMemoryBarriers[i].srcAccessMask;
+ dstAccessMask |= pImageMemoryBarriers[i].dstAccessMask;
+ }
+
+ /* Inside a renderpass, we don't know yet whether we'll be using sysmem
+ * so we have to use the sysmem flushes.
+ */
+ bool gmem = cmd->state.ccu_state == TU_CMD_CCU_GMEM &&
+ !cmd->state.pass;
+ src_flags |= vk2tu_access(srcAccessMask, gmem);
+ dst_flags |= vk2tu_access(dstAccessMask, gmem);
+
+ struct tu_cache_state *cache =
+ cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
+ tu_flush_for_access(cache, src_flags, dst_flags);
+
+ for (uint32_t i = 0; i < info->eventCount; i++) {
+ TU_FROM_HANDLE(tu_event, event, info->pEvents[i]);
+
+ tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
+
+ tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
+ CP_WAIT_REG_MEM_0_POLL_MEMORY);
+ tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
+ }
}
void
tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer,
VkPipelineStageFlags srcStageMask,
- VkPipelineStageFlags destStageMask,
- VkBool32 byRegion,
+ VkPipelineStageFlags dstStageMask,
+ VkDependencyFlags dependencyFlags,
uint32_t memoryBarrierCount,
const VkMemoryBarrier *pMemoryBarriers,
uint32_t bufferMemoryBarrierCount,
}
static void
-write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
+write_event(struct tu_cmd_buffer *cmd, struct tu_event *event,
+ VkPipelineStageFlags stageMask, unsigned value)
{
struct tu_cs *cs = &cmd->cs;
- tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
+ /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
+ assert(!cmd->state.pass);
- /* TODO: any flush required before/after ? */
+ tu_emit_cache_flush(cmd, cs);
- tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
- tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
- tu_cs_emit(cs, value);
+ tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
+
+ /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
+ * read by the CP, so the draw indirect stage counts as top-of-pipe too.
+ */
+ VkPipelineStageFlags top_of_pipe_flags =
+ VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT |
+ VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT;
+
+ if (!(stageMask & ~top_of_pipe_flags)) {
+ tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
+ tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
+ tu_cs_emit(cs, value);
+ } else {
+ /* Use a RB_DONE_TS event to wait for everything to complete. */
+ tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
+ tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
+ tu_cs_emit_qw(cs, event->bo.iova);
+ tu_cs_emit(cs, value);
+ }
}
void
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
TU_FROM_HANDLE(tu_event, event, _event);
- write_event(cmd, event, 1);
+ write_event(cmd, event, stageMask, 1);
}
void
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
TU_FROM_HANDLE(tu_event, event, _event);
- write_event(cmd, event, 0);
+ write_event(cmd, event, stageMask, 0);
}
void
const VkImageMemoryBarrier *pImageMemoryBarriers)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- struct tu_cs *cs = &cmd->cs;
-
- /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
-
- for (uint32_t i = 0; i < eventCount; i++) {
- TU_FROM_HANDLE(tu_event, event, pEvents[i]);
+ struct tu_barrier_info info;
- tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
+ info.eventCount = eventCount;
+ info.pEvents = pEvents;
+ info.srcStageMask = 0;
- tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
- tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
- CP_WAIT_REG_MEM_0_POLL_MEMORY);
- tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
- tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
- tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
- tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
- }
+ tu_barrier(cmd, memoryBarrierCount, pMemoryBarriers,
+ bufferMemoryBarrierCount, pBufferMemoryBarriers,
+ imageMemoryBarrierCount, pImageMemoryBarriers, &info);
}
void
projects / mesa.git / blobdiff