if (vk_format_is_srgb(iview->vk_format))
srgb_cntl |= (1 << i);
- const struct tu_native_format *format =
- tu6_get_native_format(iview->vk_format);
- assert(format && format->rb >= 0);
+ const struct tu_native_format format =
+ tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
tu_cs_emit_regs(cs,
A6XX_RB_MRT_BUF_INFO(i,
.color_tile_mode = tile_mode,
- .color_format = format->rb,
- .color_swap = format->swap),
+ .color_format = format.fmt,
+ .color_swap = format.swap),
A6XX_RB_MRT_PITCH(i, tu_image_stride(iview->image, iview->base_mip)),
A6XX_RB_MRT_ARRAY_PITCH(i, iview->image->layout.layer_size),
A6XX_RB_MRT_BASE(i, tu_image_view_base_ref(iview)),
tu_cs_emit_regs(cs,
A6XX_SP_FS_MRT_REG(i,
- .color_format = format->rb,
+ .color_format = format.fmt,
.color_sint = vk_format_is_sint(iview->vk_format),
.color_uint = vk_format_is_uint(iview->vk_format)));
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_INFO(.unk0 = !resolve, .gmem = !resolve));
- const struct tu_native_format *format =
- tu6_get_native_format(iview->vk_format);
- assert(format && format->rb >= 0);
+ const struct tu_native_format format =
+ tu6_format_color(iview->vk_format, iview->image->layout.tile_mode);
enum a6xx_tile_mode tile_mode =
tu6_get_image_tile_mode(iview->image, iview->base_mip);
A6XX_RB_BLIT_DST_INFO(
.tile_mode = tile_mode,
.samples = tu_msaa_samples(iview->image->samples),
- .color_format = format->rb,
- .color_swap = format->swap,
+ .color_format = format.fmt,
+ .color_swap = format.swap,
.flags = iview->image->layout.ubwc_layer_size != 0),
A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
tu_cs_emit_write_reg(cs, REG_A6XX_RB_SRGB_CNTL, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8101, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL0, 0x401);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_RENDER_CONTROL1, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_SAMPLE_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
/* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
for (uint32_t i = 0; i < eventCount; i++) {
- const struct tu_event *event = (const struct tu_event*) pEvents[i];
+ TU_FROM_HANDLE(tu_event, event, pEvents[i]);
tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);