cntl |= A6XX_RB_RENDER_CNTL_BINNING;
tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
- tu_cs_emit(cs, 0x2);
+ tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
tu_cs_emit(cs, cntl);
}
.samples = tu_msaa_samples(iview->image->samples),
.color_format = format->rb,
.color_swap = format->swap,
- .flags = iview->image->layout.ubwc_size != 0),
+ .flags = iview->image->layout.ubwc_layer_size != 0),
A6XX_RB_BLIT_DST(tu_image_view_base_ref(iview)),
A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview->image, iview->base_mip)),
A6XX_RB_BLIT_DST_ARRAY_PITCH(iview->image->layout.layer_size));
- if (iview->image->layout.ubwc_size) {
+ if (iview->image->layout.ubwc_layer_size) {
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_FLAG_DST(tu_image_view_ubwc_base_ref(iview)),
A6XX_RB_BLIT_FLAG_DST_PITCH(tu_image_view_ubwc_pitches(iview)));
static void
tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
+ struct tu_physical_device *phys_dev = cmd->device->physical_device;
+
VkResult result = tu_cs_reserve_space(cmd->device, cs, 256);
if (result != VK_SUCCESS) {
cmd->record_result = result;
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, 0x7c400004);
+ tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, phys_dev->magic.RB_CCU_CNTL_gmem);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
tu_cs_emit_regs(cs,
A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
.height = tiling->tile0.extent.height),
- A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data, .bo_offset = cmd->vsc_data_pitch));
+ A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
+ .bo_offset = 32 * cmd->vsc_data_pitch));
tu_cs_emit_regs(cs,
A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
static void
tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
+ struct tu_physical_device *phys_dev = cmd->device->physical_device;
const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
uint32_t x1 = tiling->tile0.offset.x;
update_vsc_pipe(cmd, cs);
tu_cs_emit_regs(cs,
- A6XX_PC_UNKNOWN_9805(.unknown = 0x1));
+ A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
tu_cs_emit_regs(cs,
- A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1));
+ A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, UNK_2C);
static void
tu6_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
+ struct tu_physical_device *phys_dev = cmd->device->physical_device;
+
VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
if (result != VK_SUCCESS) {
cmd->record_result = result;
tu_cs_emit_regs(cs,
A6XX_VFD_MODE_CNTL(0));
- tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = 0x1));
+ tu_cs_emit_regs(cs, A6XX_PC_UNKNOWN_9805(.unknown = phys_dev->magic.PC_UNKNOWN_9805));
- tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = 0x1));
+ tu_cs_emit_regs(cs, A6XX_SP_UNKNOWN_A0F8(.unknown = phys_dev->magic.SP_UNKNOWN_A0F8));
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
tu_cs_emit(cs, 0x1);
if (result != VK_SUCCESS)
goto fail_scratch_bo;
-#define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
-#define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
-
- /* TODO: resize on overflow or compute a max size from # of vertices in renderpass?? */
- cmd_buffer->vsc_data_pitch = 0x440 * 4;
- cmd_buffer->vsc_data2_pitch = 0x1040 * 4;
-
- result = tu_bo_init_new(device, &cmd_buffer->vsc_data, VSC_DATA_SIZE(cmd_buffer->vsc_data_pitch));
- if (result != VK_SUCCESS)
- goto fail_vsc_data;
-
- result = tu_bo_init_new(device, &cmd_buffer->vsc_data2, VSC_DATA2_SIZE(cmd_buffer->vsc_data2_pitch));
- if (result != VK_SUCCESS)
- goto fail_vsc_data2;
+ /* TODO: resize on overflow */
+ cmd_buffer->vsc_data_pitch = device->vsc_data_pitch;
+ cmd_buffer->vsc_data2_pitch = device->vsc_data2_pitch;
+ cmd_buffer->vsc_data = device->vsc_data;
+ cmd_buffer->vsc_data2 = device->vsc_data2;
return VK_SUCCESS;
-fail_vsc_data2:
- tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
-fail_vsc_data:
- tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
fail_scratch_bo:
list_del(&cmd_buffer->pool_link);
return result;
tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
{
tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
- tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data);
- tu_bo_finish(cmd_buffer->device, &cmd_buffer->vsc_data2);
list_del(&cmd_buffer->pool_link);
tu_cs_reset(cmd_buffer->device, &cmd_buffer->sub_cs);
for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
- cmd_buffer->descriptors[i].dirty = 0;
cmd_buffer->descriptors[i].valid = 0;
cmd_buffer->descriptors[i].push_dirty = false;
}
/* We don't expose robustBufferAccess, so leave the size unlimited. */
uint32_t sz = MAX_STORAGE_BUFFER_RANGE / 4;
- dst[0] = A6XX_IBO_0_FMT(TFMT6_32_UINT);
+ dst[0] = A6XX_IBO_0_FMT(FMT6_32_UINT);
dst[1] = A6XX_IBO_1_WIDTH(sz & MASK(15)) |
A6XX_IBO_1_HEIGHT(sz >> 15);
dst[2] = A6XX_IBO_2_UNK4 |
}
static void
-write_event(struct tu_cmd_buffer *cmd_buffer,
- struct tu_event *event,
- VkPipelineStageFlags stageMask,
- unsigned value)
+write_event(struct tu_cmd_buffer *cmd, struct tu_event *event, unsigned value)
{
+ struct tu_cs *cs = &cmd->cs;
+
+ VkResult result = tu_cs_reserve_space(cmd->device, cs, 4);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
+
+ tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_WRITE);
+
+ /* TODO: any flush required before/after ? */
+
+ tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
+ tu_cs_emit_qw(cs, event->bo.iova); /* ADDR_LO/HI */
+ tu_cs_emit(cs, value);
}
void
VkEvent _event,
VkPipelineStageFlags stageMask)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
TU_FROM_HANDLE(tu_event, event, _event);
- write_event(cmd_buffer, event, stageMask, 1);
+ write_event(cmd, event, 1);
}
void
VkEvent _event,
VkPipelineStageFlags stageMask)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
TU_FROM_HANDLE(tu_event, event, _event);
- write_event(cmd_buffer, event, stageMask, 0);
+ write_event(cmd, event, 0);
}
void
uint32_t imageMemoryBarrierCount,
const VkImageMemoryBarrier *pImageMemoryBarriers)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
- struct tu_barrier_info info;
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs *cs = &cmd->cs;
+
+ VkResult result = tu_cs_reserve_space(cmd->device, cs, eventCount * 7);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
- info.eventCount = eventCount;
- info.pEvents = pEvents;
- info.srcStageMask = 0;
+ /* TODO: any flush required before/after? (CP_WAIT_FOR_ME?) */
- tu_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
- bufferMemoryBarrierCount, pBufferMemoryBarriers,
- imageMemoryBarrierCount, pImageMemoryBarriers, &info);
+ for (uint32_t i = 0; i < eventCount; i++) {
+ const struct tu_event *event = (const struct tu_event*) pEvents[i];
+
+ tu_bo_list_add(&cmd->bo_list, &event->bo, MSM_SUBMIT_BO_READ);
+
+ tu_cs_emit_pkt7(cs, CP_WAIT_REG_MEM, 6);
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
+ CP_WAIT_REG_MEM_0_POLL_MEMORY);
+ tu_cs_emit_qw(cs, event->bo.iova); /* POLL_ADDR_LO/HI */
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_3_REF(1));
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_4_MASK(~0u));
+ tu_cs_emit(cs, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
+ }
}
void
projects / mesa.git / blobdiff