#include "tu_private.h"
-#include "registers/adreno_pm4.xml.h"
-#include "registers/adreno_common.xml.h"
+#include "adreno_pm4.xml.h"
+#include "adreno_common.xml.h"
#include "vk_format.h"
#include "tu_cs.h"
-#define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
-
void
tu_bo_list_init(struct tu_bo_list *list)
{
return VK_SUCCESS;
}
-static void
-tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
- const struct tu_device *dev,
- const struct tu_render_pass *pass)
-{
- const uint32_t tile_align_w = pass->tile_align_w;
- const uint32_t max_tile_width = 1024;
-
- /* note: don't offset the tiling config by render_area.offset,
- * because binning pass can't deal with it
- * this means we might end up with more tiles than necessary,
- * but load/store/etc are still scissored to the render_area
- */
- tiling->tile0.offset = (VkOffset2D) {};
-
- const uint32_t ra_width =
- tiling->render_area.extent.width +
- (tiling->render_area.offset.x - tiling->tile0.offset.x);
- const uint32_t ra_height =
- tiling->render_area.extent.height +
- (tiling->render_area.offset.y - tiling->tile0.offset.y);
-
- /* start from 1 tile */
- tiling->tile_count = (VkExtent2D) {
- .width = 1,
- .height = 1,
- };
- tiling->tile0.extent = (VkExtent2D) {
- .width = util_align_npot(ra_width, tile_align_w),
- .height = align(ra_height, TILE_ALIGN_H),
- };
-
- if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN)) {
- /* start with 2x2 tiles */
- tiling->tile_count.width = 2;
- tiling->tile_count.height = 2;
- tiling->tile0.extent.width = util_align_npot(DIV_ROUND_UP(ra_width, 2), tile_align_w);
- tiling->tile0.extent.height = align(DIV_ROUND_UP(ra_height, 2), TILE_ALIGN_H);
- }
-
- /* do not exceed max tile width */
- while (tiling->tile0.extent.width > max_tile_width) {
- tiling->tile_count.width++;
- tiling->tile0.extent.width =
- util_align_npot(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
- }
-
- /* will force to sysmem, don't bother trying to have a valid tile config
- * TODO: just skip all GMEM stuff when sysmem is forced?
- */
- if (!pass->gmem_pixels)
- return;
-
- /* do not exceed gmem size */
- while (tiling->tile0.extent.width * tiling->tile0.extent.height > pass->gmem_pixels) {
- if (tiling->tile0.extent.width > MAX2(tile_align_w, tiling->tile0.extent.height)) {
- tiling->tile_count.width++;
- tiling->tile0.extent.width =
- util_align_npot(DIV_ROUND_UP(ra_width, tiling->tile_count.width), tile_align_w);
- } else {
- /* if this assert fails then layout is impossible.. */
- assert(tiling->tile0.extent.height > TILE_ALIGN_H);
- tiling->tile_count.height++;
- tiling->tile0.extent.height =
- align(DIV_ROUND_UP(ra_height, tiling->tile_count.height), TILE_ALIGN_H);
- }
- }
-}
-
-static void
-tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
- const struct tu_device *dev)
-{
- const uint32_t max_pipe_count = 32; /* A6xx */
-
- /* start from 1 tile per pipe */
- tiling->pipe0 = (VkExtent2D) {
- .width = 1,
- .height = 1,
- };
- tiling->pipe_count = tiling->tile_count;
-
- while (tiling->pipe_count.width * tiling->pipe_count.height > max_pipe_count) {
- if (tiling->pipe0.width < tiling->pipe0.height) {
- tiling->pipe0.width += 1;
- tiling->pipe_count.width =
- DIV_ROUND_UP(tiling->tile_count.width, tiling->pipe0.width);
- } else {
- tiling->pipe0.height += 1;
- tiling->pipe_count.height =
- DIV_ROUND_UP(tiling->tile_count.height, tiling->pipe0.height);
- }
- }
-}
-
-static void
-tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
- const struct tu_device *dev)
-{
- const uint32_t max_pipe_count = 32; /* A6xx */
- const uint32_t used_pipe_count =
- tiling->pipe_count.width * tiling->pipe_count.height;
- const VkExtent2D last_pipe = {
- .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
- .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
- };
-
- assert(used_pipe_count <= max_pipe_count);
- assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
-
- for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
- for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
- const uint32_t pipe_x = tiling->pipe0.width * x;
- const uint32_t pipe_y = tiling->pipe0.height * y;
- const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
- ? last_pipe.width
- : tiling->pipe0.width;
- const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
- ? last_pipe.height
- : tiling->pipe0.height;
- const uint32_t n = tiling->pipe_count.width * y + x;
-
- tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
- A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y) |
- A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w) |
- A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h);
- tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
- }
- }
-
- memset(tiling->pipe_config + used_pipe_count, 0,
- sizeof(uint32_t) * (max_pipe_count - used_pipe_count));
-}
-
-static void
-tu_tiling_config_get_tile(const struct tu_tiling_config *tiling,
- const struct tu_device *dev,
- uint32_t tx,
- uint32_t ty,
- struct tu_tile *tile)
-{
- /* find the pipe and the slot for tile (tx, ty) */
- const uint32_t px = tx / tiling->pipe0.width;
- const uint32_t py = ty / tiling->pipe0.height;
- const uint32_t sx = tx - tiling->pipe0.width * px;
- const uint32_t sy = ty - tiling->pipe0.height * py;
- /* last pipe has different width */
- const uint32_t pipe_width =
- MIN2(tiling->pipe0.width,
- tiling->tile_count.width - px * tiling->pipe0.width);
-
- assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height);
- assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height);
- assert(sx < tiling->pipe0.width && sy < tiling->pipe0.height);
-
- /* convert to 1D indices */
- tile->pipe = tiling->pipe_count.width * py + px;
- tile->slot = pipe_width * sy + sx;
-
- /* get the blit area for the tile */
- tile->begin = (VkOffset2D) {
- .x = tiling->tile0.offset.x + tiling->tile0.extent.width * tx,
- .y = tiling->tile0.offset.y + tiling->tile0.extent.height * ty,
- };
- tile->end.x =
- (tx == tiling->tile_count.width - 1)
- ? tiling->render_area.offset.x + tiling->render_area.extent.width
- : tile->begin.x + tiling->tile0.extent.width;
- tile->end.y =
- (ty == tiling->tile_count.height - 1)
- ? tiling->render_area.offset.y + tiling->render_area.extent.height
- : tile->begin.y + tiling->tile0.extent.height;
-}
-
-enum a3xx_msaa_samples
-tu_msaa_samples(uint32_t samples)
-{
- switch (samples) {
- case 1:
- return MSAA_ONE;
- case 2:
- return MSAA_TWO;
- case 4:
- return MSAA_FOUR;
- case 8:
- return MSAA_EIGHT;
- default:
- assert(!"invalid sample count");
- return MSAA_ONE;
- }
-}
-
-static enum a4xx_index_size
-tu6_index_size(VkIndexType type)
-{
- switch (type) {
- case VK_INDEX_TYPE_UINT16:
- return INDEX4_SIZE_16_BIT;
- case VK_INDEX_TYPE_UINT32:
- return INDEX4_SIZE_32_BIT;
- default:
- unreachable("invalid VkIndexType");
- return INDEX4_SIZE_8_BIT;
- }
-}
-
void
tu6_emit_event_write(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, need_seqno ? 4 : 1);
tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
if (need_seqno) {
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova);
+ tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy));
tu_cs_emit(cs, 0);
}
}
tu6_emit_event_write(cmd_buffer, cs, CACHE_FLUSH_TS);
if (flushes & TU_CMD_FLAG_CACHE_INVALIDATE)
tu6_emit_event_write(cmd_buffer, cs, CACHE_INVALIDATE);
- if (flushes & TU_CMD_FLAG_WFI)
+ if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES)
+ tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
+ if (flushes & TU_CMD_FLAG_WAIT_FOR_IDLE)
tu_cs_emit_wfi(cs);
+ if (flushes & TU_CMD_FLAG_WAIT_FOR_ME)
+ tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
}
/* "Normal" cache flushes, that don't require any special handling */
flushes |=
TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
- TU_CMD_FLAG_WFI;
+ TU_CMD_FLAG_WAIT_FOR_IDLE;
cmd_buffer->state.cache.pending_flush_bits &= ~(
TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
- TU_CMD_FLAG_CCU_INVALIDATE_DEPTH);
+ TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
+ TU_CMD_FLAG_WAIT_FOR_IDLE);
}
tu6_emit_flushes(cmd_buffer, cs, flushes);
static void
tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
{
- const VkRect2D *render_area = &cmd->state.tiling_config.render_area;
+
+ const VkRect2D *render_area = &cmd->state.render_area;
+
+ /* Avoid assertion fails with an empty render area at (0, 0) where the
+ * subtraction below wraps around. Empty render areas should be forced to
+ * the sysmem path by use_sysmem_rendering(). It's not even clear whether
+ * an empty scissor here works, and the blob seems to force sysmem too as
+ * it sets something wrong (non-empty) for the scissor.
+ */
+ if (render_area->extent.width == 0 ||
+ render_area->extent.height == 0)
+ return;
+
uint32_t x1 = render_area->offset.x;
uint32_t y1 = render_area->offset.y;
uint32_t x2 = x1 + render_area->extent.width - 1;
A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
tu_cs_emit_regs(cs,
- A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
- A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
+ A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
+ A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
}
void
A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
}
+static void
+tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
+{
+ uint32_t enable_mask;
+ switch (id) {
+ case TU_DRAW_STATE_PROGRAM:
+ case TU_DRAW_STATE_VI:
+ case TU_DRAW_STATE_FS_CONST:
+ /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
+ * when resources would actually be used in the binning shader.
+ * Presumably the overhead of prefetching the resources isn't
+ * worth it.
+ */
+ case TU_DRAW_STATE_DESC_SETS_LOAD:
+ enable_mask = CP_SET_DRAW_STATE__0_GMEM |
+ CP_SET_DRAW_STATE__0_SYSMEM;
+ break;
+ case TU_DRAW_STATE_PROGRAM_BINNING:
+ case TU_DRAW_STATE_VI_BINNING:
+ enable_mask = CP_SET_DRAW_STATE__0_BINNING;
+ break;
+ case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM:
+ enable_mask = CP_SET_DRAW_STATE__0_GMEM;
+ break;
+ case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM:
+ enable_mask = CP_SET_DRAW_STATE__0_SYSMEM;
+ break;
+ default:
+ enable_mask = CP_SET_DRAW_STATE__0_GMEM |
+ CP_SET_DRAW_STATE__0_SYSMEM |
+ CP_SET_DRAW_STATE__0_BINNING;
+ break;
+ }
+
+ /* We need to reload the descriptors every time the descriptor sets
+ * change. However, the commands we send only depend on the pipeline
+ * because the whole point is to cache descriptors which are used by the
+ * pipeline. There's a problem here, in that the firmware has an
+ * "optimization" which skips executing groups that are set to the same
+ * value as the last draw. This means that if the descriptor sets change
+ * but not the pipeline, we'd try to re-execute the same buffer which
+ * the firmware would ignore and we wouldn't pre-load the new
+ * descriptors. Set the DIRTY bit to avoid this optimization
+ */
+ if (id == TU_DRAW_STATE_DESC_SETS_LOAD)
+ enable_mask |= CP_SET_DRAW_STATE__0_DIRTY;
+
+ tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(state.size) |
+ enable_mask |
+ CP_SET_DRAW_STATE__0_GROUP_ID(id) |
+ COND(!state.size, CP_SET_DRAW_STATE__0_DISABLE));
+ tu_cs_emit_qw(cs, state.iova);
+}
+
static bool
use_hw_binning(struct tu_cmd_buffer *cmd)
{
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+
+ /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
+ * with non-hw binning GMEM rendering. this is required because some of the
+ * XFB commands need to only be executed once
+ */
+ if (cmd->state.xfb_used)
+ return true;
if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_NOBIN))
return false;
if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_FORCEBIN))
return true;
- return (tiling->tile_count.width * tiling->tile_count.height) > 2;
+ return (fb->tile_count.width * fb->tile_count.height) > 2;
}
static bool
if (cmd->state.framebuffer->layers > 1)
return true;
- return cmd->state.tiling_config.force_sysmem;
+ /* Use sysmem for empty render areas */
+ if (cmd->state.render_area.extent.width == 0 ||
+ cmd->state.render_area.extent.height == 0)
+ return true;
+
+ if (cmd->has_tess)
+ return true;
+
+ return false;
}
static void
tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
- const struct tu_tile *tile)
+ uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot)
{
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
- const uint32_t x1 = tile->begin.x;
- const uint32_t y1 = tile->begin.y;
- const uint32_t x2 = tile->end.x - 1;
- const uint32_t y2 = tile->end.y - 1;
+ const uint32_t x1 = fb->tile0.width * tx;
+ const uint32_t y1 = fb->tile0.height * ty;
+ const uint32_t x2 = x1 + fb->tile0.width - 1;
+ const uint32_t y2 = y1 + fb->tile0.height - 1;
tu6_emit_window_scissor(cs, x1, y1, x2, y2);
tu6_emit_window_offset(cs, x1, y1);
- tu_cs_emit_regs(cs,
- A6XX_VPC_SO_OVERRIDE(.so_disable = false));
+ tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
if (use_hw_binning(cmd)) {
tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
tu_cs_emit(cs, 0x0);
- tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
- tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
- A6XX_CP_REG_TEST_0_BIT(0) |
- A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
+ tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5_OFFSET, 4);
+ tu_cs_emit(cs, fb->pipe_sizes[pipe] |
+ CP_SET_BIN_DATA5_0_VSC_N(slot));
+ tu_cs_emit(cs, pipe * cmd->vsc_draw_strm_pitch);
+ tu_cs_emit(cs, pipe * 4);
+ tu_cs_emit(cs, pipe * cmd->vsc_prim_strm_pitch);
- tu_cs_reserve(cs, 3 + 11);
- tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
- tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
- tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11));
-
- /* if (no overflow) */ {
- tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7);
- tu_cs_emit(cs, cmd->state.tiling_config.pipe_sizes[tile->pipe] |
- CP_SET_BIN_DATA5_0_VSC_N(tile->slot));
- tu_cs_emit_qw(cs, cmd->vsc_draw_strm.iova + tile->pipe * cmd->vsc_draw_strm_pitch);
- tu_cs_emit_qw(cs, cmd->vsc_draw_strm.iova + (tile->pipe * 4) + (32 * cmd->vsc_draw_strm_pitch));
- tu_cs_emit_qw(cs, cmd->vsc_prim_strm.iova + (tile->pipe * cmd->vsc_prim_strm_pitch));
-
- tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
- tu_cs_emit(cs, 0x0);
-
- /* use a NOP packet to skip over the 'else' side: */
- tu_cs_emit_pkt7(cs, CP_NOP, 2);
- } /* else */ {
- tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
- tu_cs_emit(cs, 0x1);
- }
+ tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
+ tu_cs_emit(cs, 0x0);
tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
tu_cs_emit(cs, 0x0);
struct tu_image_view *dst = fb->attachments[a].attachment;
struct tu_image_view *src = fb->attachments[gmem_a].attachment;
- tu_resolve_sysmem(cmd, cs, src, dst, fb->layers, &cmd->state.tiling_config.render_area);
+ tu_resolve_sysmem(cmd, cs, src, dst, fb->layers, &cmd->state.render_area);
}
static void
}
}
-static void
-tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index)
-{
- tu_cs_emit_regs(cs,
- A6XX_PC_RESTART_INDEX(restart_index));
-}
-
static void
tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
- const struct tu_physical_device *phys_dev = cmd->device->physical_device;
+ struct tu_device *dev = cmd->device;
+ const struct tu_physical_device *phys_dev = dev->physical_device;
tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE);
- tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff);
+ tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
+ .vs_state = true,
+ .hs_state = true,
+ .ds_state = true,
+ .gs_state = true,
+ .fs_state = true,
+ .cs_state = true,
+ .gfx_ibo = true,
+ .cs_ibo = true,
+ .gfx_shared_const = true,
+ .cs_shared_const = true,
+ .gfx_bindless = 0x1f,
+ .cs_bindless = 0x1f));
+
+ tu_cs_emit_wfi(cs);
+
+ cmd->state.cache.pending_flush_bits &=
+ ~(TU_CMD_FLAG_WAIT_FOR_IDLE | TU_CMD_FLAG_CACHE_INVALIDATE);
tu_cs_emit_regs(cs,
A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass));
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE03, 0x00000410);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BB11, 0);
+ tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_SHARED_CONSTS, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, 4);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
+ /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9101, 0xffff00);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236,
- A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0));
+ tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false));
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE,
- A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
+ tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
- tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9990, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8099, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_809B, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80A0, 2);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9981, 0x3);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9108, 0x3);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_UNKNOWN_B309, 0x000000a2);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8878, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8879, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
- /* Set not to use streamout by default, */
- tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
- tu_cs_emit(cs, 0);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
- tu_cs_emit(cs, 0);
-
tu_cs_emit_regs(cs,
A6XX_SP_HS_CTRL_REG0(0));
A6XX_RB_LRZ_CNTL(0));
tu_cs_emit_regs(cs,
- A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
+ A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = &dev->global_bo,
+ .bo_offset = gb_offset(border_color)));
tu_cs_emit_regs(cs,
- A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = &cmd->device->border_color));
+ A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = &dev->global_bo,
+ .bo_offset = gb_offset(border_color)));
+
+ /* VSC buffers:
+ * use vsc pitches from the largest values used so far with this device
+ * if there hasn't been overflow, there will already be a scratch bo
+ * allocated for these sizes
+ *
+ * if overflow is detected, the stream size is increased by 2x
+ */
+ mtx_lock(&dev->vsc_pitch_mtx);
+
+ struct tu6_global *global = dev->global_bo.map;
+
+ uint32_t vsc_draw_overflow = global->vsc_draw_overflow;
+ uint32_t vsc_prim_overflow = global->vsc_prim_overflow;
+
+ if (vsc_draw_overflow >= dev->vsc_draw_strm_pitch)
+ dev->vsc_draw_strm_pitch = (dev->vsc_draw_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
+
+ if (vsc_prim_overflow >= dev->vsc_prim_strm_pitch)
+ dev->vsc_prim_strm_pitch = (dev->vsc_prim_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
+
+ cmd->vsc_prim_strm_pitch = dev->vsc_prim_strm_pitch;
+ cmd->vsc_draw_strm_pitch = dev->vsc_draw_strm_pitch;
+
+ mtx_unlock(&dev->vsc_pitch_mtx);
+
+ struct tu_bo *vsc_bo;
+ uint32_t size0 = cmd->vsc_prim_strm_pitch * MAX_VSC_PIPES +
+ cmd->vsc_draw_strm_pitch * MAX_VSC_PIPES;
+
+ tu_get_scratch_bo(dev, size0 + MAX_VSC_PIPES * 4, &vsc_bo);
+
+ tu_cs_emit_regs(cs,
+ A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = vsc_bo, .bo_offset = size0));
+ tu_cs_emit_regs(cs,
+ A6XX_VSC_PRIM_STRM_ADDRESS(.bo = vsc_bo));
+ tu_cs_emit_regs(cs,
+ A6XX_VSC_DRAW_STRM_ADDRESS(.bo = vsc_bo,
+ .bo_offset = cmd->vsc_prim_strm_pitch * MAX_VSC_PIPES));
+
+ tu_bo_list_add(&cmd->bo_list, vsc_bo, MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
tu_cs_sanity_check(cs);
}
static void
update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
tu_cs_emit_regs(cs,
- A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
- .height = tiling->tile0.extent.height),
- A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = &cmd->vsc_draw_strm,
- .bo_offset = 32 * cmd->vsc_draw_strm_pitch));
+ A6XX_VSC_BIN_SIZE(.width = fb->tile0.width,
+ .height = fb->tile0.height));
tu_cs_emit_regs(cs,
- A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
- .ny = tiling->tile_count.height));
+ A6XX_VSC_BIN_COUNT(.nx = fb->tile_count.width,
+ .ny = fb->tile_count.height));
tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
- for (unsigned i = 0; i < 32; i++)
- tu_cs_emit(cs, tiling->pipe_config[i]);
+ tu_cs_emit_array(cs, fb->pipe_config, 32);
tu_cs_emit_regs(cs,
- A6XX_VSC_PRIM_STRM_ADDRESS(.bo = &cmd->vsc_prim_strm),
A6XX_VSC_PRIM_STRM_PITCH(cmd->vsc_prim_strm_pitch),
- A6XX_VSC_PRIM_STRM_ARRAY_PITCH(cmd->vsc_prim_strm.size));
+ A6XX_VSC_PRIM_STRM_LIMIT(cmd->vsc_prim_strm_pitch - VSC_PAD));
tu_cs_emit_regs(cs,
- A6XX_VSC_DRAW_STRM_ADDRESS(.bo = &cmd->vsc_draw_strm),
A6XX_VSC_DRAW_STRM_PITCH(cmd->vsc_draw_strm_pitch),
- A6XX_VSC_DRAW_STRM_ARRAY_PITCH(cmd->vsc_draw_strm.size));
+ A6XX_VSC_DRAW_STRM_LIMIT(cmd->vsc_draw_strm_pitch - VSC_PAD));
}
static void
emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
const uint32_t used_pipe_count =
- tiling->pipe_count.width * tiling->pipe_count.height;
-
- /* Clear vsc_scratch: */
- tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
- tu_cs_emit(cs, 0x0);
+ fb->pipe_count.width * fb->pipe_count.height;
- /* Check for overflow, write vsc_scratch if detected: */
for (int i = 0; i < used_pipe_count; i++) {
tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
- tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch));
+ tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch - VSC_PAD));
tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
- tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(1 + cmd->vsc_draw_strm_pitch));
+ tu_cs_emit_qw(cs, global_iova(cmd, vsc_draw_overflow));
+ tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_draw_strm_pitch));
tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
- tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch));
+ tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch - VSC_PAD));
tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
- tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(3 + cmd->vsc_prim_strm_pitch));
+ tu_cs_emit_qw(cs, global_iova(cmd, vsc_prim_overflow));
+ tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_prim_strm_pitch));
}
tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
-
- tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
-
- tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
- tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
- CP_MEM_TO_REG_0_CNT(1 - 1));
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_scratch));
-
- /*
- * This is a bit awkward, we really want a way to invert the
- * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
- * execute cmds to use hwbinning when a bit is *not* set. This
- * dance is to invert OVERFLOW_FLAG_REG
- *
- * A CP_NOP packet is used to skip executing the 'else' clause
- * if (b0 set)..
- */
-
- /* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
- tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
- tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
- A6XX_CP_REG_TEST_0_BIT(0) |
- A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
-
- tu_cs_reserve(cs, 3 + 7);
- tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
- tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
- tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7));
-
- /* if (b0 set) */ {
- /*
- * On overflow, mirror the value to control->vsc_overflow
- * which CPU is checking to detect overflow (see
- * check_vsc_overflow())
- */
- tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
- tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
- CP_REG_TO_MEM_0_CNT(0));
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova + ctrl_offset(vsc_overflow));
-
- tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
- tu_cs_emit(cs, 0x0);
-
- tu_cs_emit_pkt7(cs, CP_NOP, 2); /* skip 'else' when 'if' is taken */
- } /* else */ {
- tu_cs_emit_pkt4(cs, OVERFLOW_FLAG_REG, 1);
- tu_cs_emit(cs, 0x1);
- }
}
static void
tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
struct tu_physical_device *phys_dev = cmd->device->physical_device;
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
-
- uint32_t x1 = tiling->tile0.offset.x;
- uint32_t y1 = tiling->tile0.offset.y;
- uint32_t x2 = tiling->render_area.offset.x + tiling->render_area.extent.width - 1;
- uint32_t y2 = tiling->render_area.offset.y + tiling->render_area.extent.height - 1;
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
- tu6_emit_window_scissor(cs, x1, y1, x2, y2);
+ tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
tu_cs_emit(cs, 0x0);
}
+static struct tu_draw_state
+tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
+ const struct tu_subpass *subpass,
+ bool gmem)
+{
+ /* note: we can probably emit input attachments just once for the whole
+ * renderpass, this would avoid emitting both sysmem/gmem versions
+ *
+ * emit two texture descriptors for each input, as a workaround for
+ * d24s8, which can be sampled as both float (depth) and integer (stencil)
+ * tu_shader lowers uint input attachment loads to use the 2nd descriptor
+ * in the pair
+ * TODO: a smarter workaround
+ */
+
+ if (!subpass->input_count)
+ return (struct tu_draw_state) {};
+
+ struct tu_cs_memory texture;
+ VkResult result = tu_cs_alloc(&cmd->sub_cs, subpass->input_count * 2,
+ A6XX_TEX_CONST_DWORDS, &texture);
+ assert(result == VK_SUCCESS);
+
+ for (unsigned i = 0; i < subpass->input_count * 2; i++) {
+ uint32_t a = subpass->input_attachments[i / 2].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ struct tu_image_view *iview =
+ cmd->state.framebuffer->attachments[a].attachment;
+ const struct tu_render_pass_attachment *att =
+ &cmd->state.pass->attachments[a];
+ uint32_t *dst = &texture.map[A6XX_TEX_CONST_DWORDS * i];
+
+ memcpy(dst, iview->descriptor, A6XX_TEX_CONST_DWORDS * 4);
+
+ if (i % 2 == 1 && att->format == VK_FORMAT_D24_UNORM_S8_UINT) {
+ /* note this works because spec says fb and input attachments
+ * must use identity swizzle
+ */
+ dst[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK |
+ A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
+ A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
+ dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT) |
+ A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y) |
+ A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
+ A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO) |
+ A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE);
+ }
+
+ if (!gmem)
+ continue;
+
+ /* patched for gmem */
+ dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
+ dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
+ dst[2] =
+ A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
+ A6XX_TEX_CONST_2_PITCH(cmd->state.framebuffer->tile0.width * att->cpp);
+ dst[3] = 0;
+ dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
+ dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
+ for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
+ dst[i] = 0;
+ }
+
+ struct tu_cs cs;
+ struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 9);
+
+ tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3);
+ tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
+ CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
+ CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX) |
+ CP_LOAD_STATE6_0_NUM_UNIT(subpass->input_count * 2));
+ tu_cs_emit_qw(&cs, texture.iova);
+
+ tu_cs_emit_pkt4(&cs, REG_A6XX_SP_FS_TEX_CONST_LO, 2);
+ tu_cs_emit_qw(&cs, texture.iova);
+
+ tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
+
+ assert(cs.cur == cs.end); /* validate draw state size */
+
+ return ds;
+}
+
static void
-tu_emit_load_clear(struct tu_cmd_buffer *cmd,
- const VkRenderPassBeginInfo *info)
+tu_set_input_attachments(struct tu_cmd_buffer *cmd, const struct tu_subpass *subpass)
+{
+ struct tu_cs *cs = &cmd->draw_cs;
+
+ tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 6);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
+ tu_emit_input_attachments(cmd, subpass, true));
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
+ tu_emit_input_attachments(cmd, subpass, false));
+}
+
+static void
+tu_emit_renderpass_begin(struct tu_cmd_buffer *cmd,
+ const VkRenderPassBeginInfo *info)
{
struct tu_cs *cs = &cmd->draw_cs;
}
static void
-tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
- const struct VkRect2D *renderArea)
+tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
const struct tu_framebuffer *fb = cmd->state.framebuffer;
tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM);
/* enable stream-out, with sysmem there is only one pass: */
- tu_cs_emit_regs(cs,
- A6XX_VPC_SO_OVERRIDE(.so_disable = false));
+ tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
tu_cs_emit(cs, 0x1);
tu_cs_sanity_check(cs);
}
-
static void
tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_GMEM);
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
if (use_hw_binning(cmd)) {
/* enable stream-out during binning pass: */
- tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
+ tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
- tu6_emit_bin_size(cs,
- tiling->tile0.extent.width,
- tiling->tile0.extent.height,
+ tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
tu6_emit_binning_pass(cmd, cs);
/* and disable stream-out for draw pass: */
- tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=true));
+ tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
- tu6_emit_bin_size(cs,
- tiling->tile0.extent.width,
- tiling->tile0.extent.height,
+ tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height,
A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
tu_cs_emit_regs(cs,
tu_cs_emit(cs, 0x1);
} else {
/* no binning pass, so enable stream-out for draw pass:: */
- tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false));
+ tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
- tu6_emit_bin_size(cs,
- tiling->tile0.extent.width,
- tiling->tile0.extent.height,
- 0x6000000);
+ tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, 0x6000000);
}
tu_cs_sanity_check(cs);
}
static void
-tu6_render_tile(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- const struct tu_tile *tile)
+tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
- tu6_emit_tile_select(cmd, cs, tile);
-
tu_cs_emit_call(cs, &cmd->draw_cs);
if (use_hw_binning(cmd)) {
- tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
- tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
- A6XX_CP_REG_TEST_0_BIT(0) |
- A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
-
- tu_cs_reserve(cs, 3 + 2);
- tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
- tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
- tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(2));
-
- /* if (no overflow) */ {
- tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
- tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
- }
+ tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
}
tu_cs_emit_ib(cs, &cmd->state.tile_store_ib);
static void
tu_cmd_render_tiles(struct tu_cmd_buffer *cmd)
{
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
tu6_tile_render_begin(cmd, &cmd->cs);
- for (uint32_t y = 0; y < tiling->tile_count.height; y++) {
- for (uint32_t x = 0; x < tiling->tile_count.width; x++) {
- struct tu_tile tile;
- tu_tiling_config_get_tile(tiling, cmd->device, x, y, &tile);
- tu6_render_tile(cmd, &cmd->cs, &tile);
+ uint32_t pipe = 0;
+ for (uint32_t py = 0; py < fb->pipe_count.height; py++) {
+ for (uint32_t px = 0; px < fb->pipe_count.width; px++, pipe++) {
+ uint32_t tx1 = px * fb->pipe0.width;
+ uint32_t ty1 = py * fb->pipe0.height;
+ uint32_t tx2 = MIN2(tx1 + fb->pipe0.width, fb->tile_count.width);
+ uint32_t ty2 = MIN2(ty1 + fb->pipe0.height, fb->tile_count.height);
+ uint32_t slot = 0;
+ for (uint32_t ty = ty1; ty < ty2; ty++) {
+ for (uint32_t tx = tx1; tx < tx2; tx++, slot++) {
+ tu6_emit_tile_select(cmd, &cmd->cs, tx, ty, pipe, slot);
+ tu6_render_tile(cmd, &cmd->cs);
+ }
+ }
}
}
static void
tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd)
{
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
-
- tu6_sysmem_render_begin(cmd, &cmd->cs, &tiling->render_area);
+ tu6_sysmem_render_begin(cmd, &cmd->cs);
tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
cmd->state.tile_store_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
}
-static void
-tu_cmd_update_tiling_config(struct tu_cmd_buffer *cmd,
- const VkRect2D *render_area)
-{
- const struct tu_device *dev = cmd->device;
- struct tu_tiling_config *tiling = &cmd->state.tiling_config;
-
- tiling->render_area = *render_area;
- tiling->force_sysmem = false;
-
- tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass);
- tu_tiling_config_update_pipe_layout(tiling, dev);
- tu_tiling_config_update_pipes(tiling, dev);
-}
-
-const struct tu_dynamic_state default_dynamic_state = {
- .viewport =
- {
- .count = 0,
- },
- .scissor =
- {
- .count = 0,
- },
- .line_width = 1.0f,
- .depth_bias =
- {
- .bias = 0.0f,
- .clamp = 0.0f,
- .slope = 0.0f,
- },
- .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
- .depth_bounds =
- {
- .min = 0.0f,
- .max = 1.0f,
- },
- .stencil_compare_mask =
- {
- .front = ~0u,
- .back = ~0u,
- },
- .stencil_write_mask =
- {
- .front = ~0u,
- .back = ~0u,
- },
- .stencil_reference =
- {
- .front = 0u,
- .back = 0u,
- },
-};
-
-static void UNUSED /* FINISHME */
-tu_bind_dynamic_state(struct tu_cmd_buffer *cmd_buffer,
- const struct tu_dynamic_state *src)
-{
- struct tu_dynamic_state *dest = &cmd_buffer->state.dynamic;
- uint32_t copy_mask = src->mask;
- uint32_t dest_mask = 0;
-
- tu_use_args(cmd_buffer); /* FINISHME */
-
- /* Make sure to copy the number of viewports/scissors because they can
- * only be specified at pipeline creation time.
- */
- dest->viewport.count = src->viewport.count;
- dest->scissor.count = src->scissor.count;
- dest->discard_rectangle.count = src->discard_rectangle.count;
-
- if (copy_mask & TU_DYNAMIC_VIEWPORT) {
- if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
- src->viewport.count * sizeof(VkViewport))) {
- typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
- src->viewport.count);
- dest_mask |= TU_DYNAMIC_VIEWPORT;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_SCISSOR) {
- if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
- src->scissor.count * sizeof(VkRect2D))) {
- typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
- src->scissor.count);
- dest_mask |= TU_DYNAMIC_SCISSOR;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_LINE_WIDTH) {
- if (dest->line_width != src->line_width) {
- dest->line_width = src->line_width;
- dest_mask |= TU_DYNAMIC_LINE_WIDTH;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_DEPTH_BIAS) {
- if (memcmp(&dest->depth_bias, &src->depth_bias,
- sizeof(src->depth_bias))) {
- dest->depth_bias = src->depth_bias;
- dest_mask |= TU_DYNAMIC_DEPTH_BIAS;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_BLEND_CONSTANTS) {
- if (memcmp(&dest->blend_constants, &src->blend_constants,
- sizeof(src->blend_constants))) {
- typed_memcpy(dest->blend_constants, src->blend_constants, 4);
- dest_mask |= TU_DYNAMIC_BLEND_CONSTANTS;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_DEPTH_BOUNDS) {
- if (memcmp(&dest->depth_bounds, &src->depth_bounds,
- sizeof(src->depth_bounds))) {
- dest->depth_bounds = src->depth_bounds;
- dest_mask |= TU_DYNAMIC_DEPTH_BOUNDS;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_STENCIL_COMPARE_MASK) {
- if (memcmp(&dest->stencil_compare_mask, &src->stencil_compare_mask,
- sizeof(src->stencil_compare_mask))) {
- dest->stencil_compare_mask = src->stencil_compare_mask;
- dest_mask |= TU_DYNAMIC_STENCIL_COMPARE_MASK;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_STENCIL_WRITE_MASK) {
- if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
- sizeof(src->stencil_write_mask))) {
- dest->stencil_write_mask = src->stencil_write_mask;
- dest_mask |= TU_DYNAMIC_STENCIL_WRITE_MASK;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_STENCIL_REFERENCE) {
- if (memcmp(&dest->stencil_reference, &src->stencil_reference,
- sizeof(src->stencil_reference))) {
- dest->stencil_reference = src->stencil_reference;
- dest_mask |= TU_DYNAMIC_STENCIL_REFERENCE;
- }
- }
-
- if (copy_mask & TU_DYNAMIC_DISCARD_RECTANGLE) {
- if (memcmp(&dest->discard_rectangle.rectangles,
- &src->discard_rectangle.rectangles,
- src->discard_rectangle.count * sizeof(VkRect2D))) {
- typed_memcpy(dest->discard_rectangle.rectangles,
- src->discard_rectangle.rectangles,
- src->discard_rectangle.count);
- dest_mask |= TU_DYNAMIC_DISCARD_RECTANGLE;
- }
- }
-}
-
static VkResult
tu_create_cmd_buffer(struct tu_device *device,
struct tu_cmd_pool *pool,
VkCommandBuffer *pCommandBuffer)
{
struct tu_cmd_buffer *cmd_buffer;
- cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
- VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
+
+ cmd_buffer = vk_object_zalloc(&device->vk, NULL, sizeof(*cmd_buffer),
+ VK_OBJECT_TYPE_COMMAND_BUFFER);
if (cmd_buffer == NULL)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
- cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
cmd_buffer->device = device;
cmd_buffer->pool = pool;
cmd_buffer->level = level;
list_inithead(&cmd_buffer->upload.list);
- VkResult result = tu_bo_init_new(device, &cmd_buffer->scratch_bo, 0x1000);
- if (result != VK_SUCCESS)
- goto fail_scratch_bo;
-
- /* TODO: resize on overflow */
- cmd_buffer->vsc_draw_strm_pitch = device->vsc_draw_strm_pitch;
- cmd_buffer->vsc_prim_strm_pitch = device->vsc_prim_strm_pitch;
- cmd_buffer->vsc_draw_strm = device->vsc_draw_strm;
- cmd_buffer->vsc_prim_strm = device->vsc_prim_strm;
-
return VK_SUCCESS;
-
-fail_scratch_bo:
- list_del(&cmd_buffer->pool_link);
- return result;
}
static void
tu_cmd_buffer_destroy(struct tu_cmd_buffer *cmd_buffer)
{
- tu_bo_finish(cmd_buffer->device, &cmd_buffer->scratch_bo);
-
list_del(&cmd_buffer->pool_link);
- for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
- free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
-
tu_cs_finish(&cmd_buffer->cs);
tu_cs_finish(&cmd_buffer->draw_cs);
tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
tu_cs_finish(&cmd_buffer->sub_cs);
tu_bo_list_destroy(&cmd_buffer->bo_list);
- vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
+ vk_object_free(&cmd_buffer->device->vk, &cmd_buffer->pool->alloc, cmd_buffer);
}
static VkResult
tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
tu_cs_reset(&cmd_buffer->sub_cs);
- for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
- cmd_buffer->descriptors[i].valid = 0;
- cmd_buffer->descriptors[i].push_dirty = false;
- }
+ for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
+ memset(&cmd_buffer->descriptors[i].sets, 0, sizeof(cmd_buffer->descriptors[i].sets));
cmd_buffer->status = TU_CMD_BUFFER_STATUS_INITIAL;
list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
result = tu_reset_cmd_buffer(cmd_buffer);
- cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
cmd_buffer->level = pAllocateInfo->level;
pCommandBuffers[i] = tu_cmd_buffer_to_handle(cmd_buffer);
}
memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
+ cmd_buffer->state.index_size = 0xff; /* dirty restart index */
+
tu_cache_init(&cmd_buffer->state.cache);
tu_cache_init(&cmd_buffer->state.renderpass_cache);
cmd_buffer->usage_flags = pBeginInfo->flags;
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
TU_FROM_HANDLE(tu_buffer, buf, buffer);
- /* initialize/update the restart index */
- if (!cmd->state.index_buffer || cmd->state.index_type != indexType) {
- struct tu_cs *draw_cs = &cmd->draw_cs;
- tu6_emit_restart_index(
- draw_cs, indexType == VK_INDEX_TYPE_UINT32 ? 0xffffffff : 0xffff);
- tu_cs_sanity_check(draw_cs);
+ uint32_t index_size, index_shift, restart_index;
+
+ switch (indexType) {
+ case VK_INDEX_TYPE_UINT16:
+ index_size = INDEX4_SIZE_16_BIT;
+ index_shift = 1;
+ restart_index = 0xffff;
+ break;
+ case VK_INDEX_TYPE_UINT32:
+ index_size = INDEX4_SIZE_32_BIT;
+ index_shift = 2;
+ restart_index = 0xffffffff;
+ break;
+ case VK_INDEX_TYPE_UINT8_EXT:
+ index_size = INDEX4_SIZE_8_BIT;
+ index_shift = 0;
+ restart_index = 0xff;
+ break;
+ default:
+ unreachable("invalid VkIndexType");
}
- /* track the BO */
- if (cmd->state.index_buffer != buf)
- tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
+ /* initialize/update the restart index */
+ if (cmd->state.index_size != index_size)
+ tu_cs_emit_regs(&cmd->draw_cs, A6XX_PC_RESTART_INDEX(restart_index));
+
+ assert(buf->size >= offset);
+
+ cmd->state.index_va = buf->bo->iova + buf->bo_offset + offset;
+ cmd->state.max_index_count = (buf->size - offset) >> index_shift;
+ cmd->state.index_size = index_size;
- cmd->state.index_buffer = buf;
- cmd->state.index_offset = offset;
- cmd->state.index_type = indexType;
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
}
void
TU_FROM_HANDLE(tu_descriptor_set, set, pDescriptorSets[i]);
descriptors_state->sets[idx] = set;
- descriptors_state->valid |= (1u << idx);
-
- /* Note: the actual input attachment indices come from the shader
- * itself, so we can't generate the patched versions of these until
- * draw time when both the pipeline and descriptors are bound and
- * we're inside the render pass.
- */
- unsigned dst_idx = layout->set[idx].input_attachment_start;
- memcpy(&descriptors_state->input_attachments[dst_idx * A6XX_TEX_CONST_DWORDS],
- set->dynamic_descriptors,
- set->layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
- /* Dynamic buffers come after input attachments in the descriptor set
- * itself, but due to how the Vulkan descriptor set binding works, we
- * have to put input attachments and dynamic buffers in separate
- * buffers in the descriptor_state and then combine them at draw
- * time. Binding a descriptor set only invalidates the descriptor
- * sets after it, but if we try to tightly pack the descriptors after
- * the input attachments then we could corrupt dynamic buffers in the
- * descriptor set before it, or we'd have to move all the dynamic
- * buffers over. We just put them into separate buffers to make
- * binding as well as the later patching of input attachments easy.
- */
- unsigned src_idx = j + set->layout->input_attachment_count;
+ /* update the contents of the dynamic descriptor set */
+ unsigned src_idx = j;
unsigned dst_idx = j + layout->set[idx].dynamic_offset_start;
assert(dyn_idx < dynamicOffsetCount);
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
}
}
+ assert(dyn_idx == dynamicOffsetCount);
- if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE)
- cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS;
- else
- cmd->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS | TU_CMD_DIRTY_SHADER_CONSTS;
-}
+ uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg, hlsq_invalidate_value;
+ uint64_t addr[MAX_SETS + 1] = {};
+ struct tu_cs *cs, state_cs;
-void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
- uint32_t firstBinding,
- uint32_t bindingCount,
+ for (uint32_t i = 0; i < MAX_SETS; i++) {
+ struct tu_descriptor_set *set = descriptors_state->sets[i];
+ if (set)
+ addr[i] = set->va | 3;
+ }
+
+ if (layout->dynamic_offset_count) {
+ /* allocate and fill out dynamic descriptor set */
+ struct tu_cs_memory dynamic_desc_set;
+ VkResult result = tu_cs_alloc(&cmd->sub_cs, layout->dynamic_offset_count,
+ A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
+ assert(result == VK_SUCCESS);
+
+ memcpy(dynamic_desc_set.map, descriptors_state->dynamic_descriptors,
+ layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
+ addr[MAX_SETS] = dynamic_desc_set.iova | 3;
+ }
+
+ if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS) {
+ sp_bindless_base_reg = REG_A6XX_SP_BINDLESS_BASE(0);
+ hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
+ hlsq_invalidate_value = A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
+
+ cmd->state.desc_sets = tu_cs_draw_state(&cmd->sub_cs, &state_cs, 24);
+ cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS_LOAD | TU_CMD_DIRTY_SHADER_CONSTS;
+ cs = &state_cs;
+ } else {
+ assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE);
+
+ sp_bindless_base_reg = REG_A6XX_SP_CS_BINDLESS_BASE(0);
+ hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
+ hlsq_invalidate_value = A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
+
+ cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
+ cs = &cmd->cs;
+ }
+
+ tu_cs_emit_pkt4(cs, sp_bindless_base_reg, 10);
+ tu_cs_emit_array(cs, (const uint32_t*) addr, 10);
+ tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg, 10);
+ tu_cs_emit_array(cs, (const uint32_t*) addr, 10);
+ tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(.dword = hlsq_invalidate_value));
+
+ if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS) {
+ assert(cs->cur == cs->end); /* validate draw state size */
+ tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
+ tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
+ }
+}
+
+void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
+ uint32_t firstBinding,
+ uint32_t bindingCount,
const VkBuffer *pBuffers,
const VkDeviceSize *pOffsets,
const VkDeviceSize *pSizes)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- assert(firstBinding + bindingCount <= IR3_MAX_SO_BUFFERS);
+ struct tu_cs *cs = &cmd->draw_cs;
+
+ /* using COND_REG_EXEC for xfb commands matches the blob behavior
+ * presumably there isn't any benefit using a draw state when the
+ * condition is (SYSMEM | BINNING)
+ */
+ tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
+ CP_COND_REG_EXEC_0_SYSMEM |
+ CP_COND_REG_EXEC_0_BINNING);
for (uint32_t i = 0; i < bindingCount; i++) {
- uint32_t idx = firstBinding + i;
TU_FROM_HANDLE(tu_buffer, buf, pBuffers[i]);
+ uint64_t iova = buf->bo->iova + pOffsets[i];
+ uint32_t size = buf->bo->size - pOffsets[i];
+ uint32_t idx = i + firstBinding;
- if (pOffsets[i] != 0)
- cmd->state.streamout_reset |= 1 << idx;
+ if (pSizes && pSizes[i] != VK_WHOLE_SIZE)
+ size = pSizes[i];
- cmd->state.streamout_buf.buffers[idx] = buf;
- cmd->state.streamout_buf.offsets[idx] = pOffsets[i];
- cmd->state.streamout_buf.sizes[idx] = pSizes[i];
+ /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
+ uint32_t offset = iova & 0x1f;
+ iova &= ~(uint64_t) 0x1f;
+
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE(idx), 3);
+ tu_cs_emit_qw(cs, iova);
+ tu_cs_emit(cs, size + offset);
- cmd->state.streamout_enabled |= 1 << idx;
+ cmd->state.streamout_offset[idx] = offset;
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_WRITE);
}
- cmd->state.dirty |= TU_CMD_DIRTY_STREAMOUT_BUFFERS;
+ tu_cond_exec_end(cs);
}
-void tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
- uint32_t firstCounterBuffer,
- uint32_t counterBufferCount,
- const VkBuffer *pCounterBuffers,
- const VkDeviceSize *pCounterBufferOffsets)
+void
+tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
+ uint32_t firstCounterBuffer,
+ uint32_t counterBufferCount,
+ const VkBuffer *pCounterBuffers,
+ const VkDeviceSize *pCounterBufferOffsets)
{
- assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
- /* TODO do something with counter buffer? */
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs *cs = &cmd->draw_cs;
+
+ tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
+ CP_COND_REG_EXEC_0_SYSMEM |
+ CP_COND_REG_EXEC_0_BINNING);
+
+ /* TODO: only update offset for active buffers */
+ for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++)
+ tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i]));
+
+ for (uint32_t i = 0; i < counterBufferCount; i++) {
+ uint32_t idx = firstCounterBuffer + i;
+ uint32_t offset = cmd->state.streamout_offset[idx];
+
+ if (!pCounterBuffers[i])
+ continue;
+
+ TU_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
+
+ tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
+ tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
+ CP_MEM_TO_REG_0_UNK31 |
+ CP_MEM_TO_REG_0_CNT(1));
+ tu_cs_emit_qw(cs, buf->bo->iova + pCounterBufferOffsets[i]);
+
+ if (offset) {
+ tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
+ tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
+ CP_REG_RMW_0_SRC1_ADD);
+ tu_cs_emit_qw(cs, 0xffffffff);
+ tu_cs_emit_qw(cs, offset);
+ }
+ }
+
+ tu_cond_exec_end(cs);
}
void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
const VkBuffer *pCounterBuffers,
const VkDeviceSize *pCounterBufferOffsets)
{
- assert(firstCounterBuffer + counterBufferCount <= IR3_MAX_SO_BUFFERS);
- /* TODO do something with counter buffer? */
-
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- cmd->state.streamout_enabled = 0;
+ struct tu_cs *cs = &cmd->draw_cs;
+
+ tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
+ CP_COND_REG_EXEC_0_SYSMEM |
+ CP_COND_REG_EXEC_0_BINNING);
+
+ /* TODO: only flush buffers that need to be flushed */
+ for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
+ /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
+ tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
+ tu_cs_emit_qw(cs, global_iova(cmd, flush_base[i]));
+ tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i);
+ }
+
+ for (uint32_t i = 0; i < counterBufferCount; i++) {
+ uint32_t idx = firstCounterBuffer + i;
+ uint32_t offset = cmd->state.streamout_offset[idx];
+
+ if (!pCounterBuffers[i])
+ continue;
+
+ TU_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_WRITE);
+
+ /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
+ tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
+ tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
+ CP_MEM_TO_REG_0_SHIFT_BY_2 |
+ 0x40000 | /* ??? */
+ CP_MEM_TO_REG_0_UNK31 |
+ CP_MEM_TO_REG_0_CNT(1));
+ tu_cs_emit_qw(cs, global_iova(cmd, flush_base[idx]));
+
+ if (offset) {
+ tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
+ tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
+ CP_REG_RMW_0_SRC1_ADD);
+ tu_cs_emit_qw(cs, 0xffffffff);
+ tu_cs_emit_qw(cs, -offset);
+ }
+
+ tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
+ tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
+ CP_REG_TO_MEM_0_CNT(1));
+ tu_cs_emit_qw(cs, buf->bo->iova + pCounterBufferOffsets[i]);
+ }
+
+ tu_cond_exec_end(cs);
+
+ cmd->state.xfb_used = true;
}
void
tu_emit_cache_flush(cmd_buffer, &cmd_buffer->cs);
}
- tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->scratch_bo,
- MSM_SUBMIT_BO_WRITE);
-
- if (cmd_buffer->use_vsc_data) {
- tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_draw_strm,
- MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
- tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->vsc_prim_strm,
- MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
- }
-
- tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->device->border_color,
- MSM_SUBMIT_BO_READ);
+ tu_bo_list_add(&cmd_buffer->bo_list, &cmd_buffer->device->global_bo,
+ MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
for (uint32_t i = 0; i < cmd_buffer->draw_cs.bo_count; i++) {
tu_bo_list_add(&cmd_buffer->bo_list, cmd_buffer->draw_cs.bos[i],
return cmd_buffer->record_result;
}
+static struct tu_cs
+tu_cmd_dynamic_state(struct tu_cmd_buffer *cmd, uint32_t id, uint32_t size)
+{
+ struct tu_cs cs;
+
+ assert(id < ARRAY_SIZE(cmd->state.dynamic_state));
+ cmd->state.dynamic_state[id] = tu_cs_draw_state(&cmd->sub_cs, &cs, size);
+
+ tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
+ tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DYNAMIC + id, cmd->state.dynamic_state[id]);
+
+ return cs;
+}
+
void
tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
VkPipelineBindPoint pipelineBindPoint,
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
- tu_bo_list_add(&cmd->bo_list, &pipeline->program.binary_bo,
- MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
for (uint32_t i = 0; i < pipeline->cs.bo_count; i++) {
tu_bo_list_add(&cmd->bo_list, pipeline->cs.bos[i],
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE) {
cmd->state.compute_pipeline = pipeline;
- cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_PIPELINE;
+ tu_cs_emit_state_ib(&cmd->cs, pipeline->program.state);
return;
}
assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS);
cmd->state.pipeline = pipeline;
- cmd->state.dirty |= TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_SHADER_CONSTS;
+ cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS_LOAD | TU_CMD_DIRTY_SHADER_CONSTS;
+
+ struct tu_cs *cs = &cmd->draw_cs;
+ uint32_t mask = ~pipeline->dynamic_state_mask & BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT);
+ uint32_t i;
+
+ tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (7 + util_bitcount(mask)));
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS, pipeline->ds_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state);
+ for_each_bit(i, mask)
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, pipeline->dynamic_state[i]);
/* If the new pipeline requires more VBs than we had previously set up, we
* need to re-emit them in SDS. If it requires the same set or fewer, we
if (pipeline->vi.bindings_used & ~cmd->vertex_bindings_set)
cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
- /* If the pipeline needs a dynamic descriptor, re-emit descriptor sets */
- if (pipeline->layout->dynamic_offset_count + pipeline->layout->input_attachment_count)
- cmd->state.dirty |= TU_CMD_DIRTY_DESCRIPTOR_SETS;
+ /* dynamic linewidth state depends pipeline state's gras_su_cntl
+ * so the dynamic state ib must be updated when pipeline changes
+ */
+ if (pipeline->dynamic_state_mask & BIT(VK_DYNAMIC_STATE_LINE_WIDTH)) {
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_LINE_WIDTH, 2);
+
+ cmd->state.dynamic_gras_su_cntl &= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
+ cmd->state.dynamic_gras_su_cntl |= pipeline->gras_su_cntl;
+
+ tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = cmd->state.dynamic_gras_su_cntl));
+ }
}
void
const VkViewport *pViewports)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_VIEWPORT, 18);
assert(firstViewport == 0 && viewportCount == 1);
- cmd->state.dynamic.viewport.viewports[0] = pViewports[0];
- cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_VIEWPORT;
+
+ tu6_emit_viewport(&cs, pViewports);
}
void
const VkRect2D *pScissors)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_SCISSOR, 3);
assert(firstScissor == 0 && scissorCount == 1);
- cmd->state.dynamic.scissor.scissors[0] = pScissors[0];
- cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_SCISSOR;
+
+ tu6_emit_scissor(&cs, pScissors);
}
void
tu_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_LINE_WIDTH, 2);
- cmd->state.dynamic.line_width = lineWidth;
+ cmd->state.dynamic_gras_su_cntl &= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
+ cmd->state.dynamic_gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth / 2.0f);
- /* line width depends on VkPipelineRasterizationStateCreateInfo */
- cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
+ tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = cmd->state.dynamic_gras_su_cntl));
}
void
float depthBiasSlopeFactor)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- struct tu_cs *draw_cs = &cmd->draw_cs;
-
- tu6_emit_depth_bias(draw_cs, depthBiasConstantFactor, depthBiasClamp,
- depthBiasSlopeFactor);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BIAS, 4);
- tu_cs_sanity_check(draw_cs);
+ tu6_emit_depth_bias(&cs, depthBiasConstantFactor, depthBiasClamp, depthBiasSlopeFactor);
}
void
const float blendConstants[4])
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
- struct tu_cs *draw_cs = &cmd->draw_cs;
-
- tu6_emit_blend_constants(draw_cs, blendConstants);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5);
- tu_cs_sanity_check(draw_cs);
+ tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
+ tu_cs_emit_array(&cs, (const uint32_t *) blendConstants, 4);
}
void
float minDepthBounds,
float maxDepthBounds)
{
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3);
+
+ tu_cs_emit_regs(&cs,
+ A6XX_RB_Z_BOUNDS_MIN(minDepthBounds),
+ A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds));
+}
+
+static void
+update_stencil_mask(uint32_t *value, VkStencilFaceFlags face, uint32_t mask)
+{
+ if (face & VK_STENCIL_FACE_FRONT_BIT)
+ *value = (*value & 0xff00) | (mask & 0xff);
+ if (face & VK_STENCIL_FACE_BACK_BIT)
+ *value = (*value & 0xff) | (mask & 0xff) << 8;
}
void
uint32_t compareMask)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2);
- if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
- cmd->state.dynamic.stencil_compare_mask.front = compareMask;
- if (faceMask & VK_STENCIL_FACE_BACK_BIT)
- cmd->state.dynamic.stencil_compare_mask.back = compareMask;
+ update_stencil_mask(&cmd->state.dynamic_stencil_mask, faceMask, compareMask);
- /* the front/back compare masks must be updated together */
- cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
+ tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.dword = cmd->state.dynamic_stencil_mask));
}
void
uint32_t writeMask)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK, 2);
- if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
- cmd->state.dynamic.stencil_write_mask.front = writeMask;
- if (faceMask & VK_STENCIL_FACE_BACK_BIT)
- cmd->state.dynamic.stencil_write_mask.back = writeMask;
+ update_stencil_mask(&cmd->state.dynamic_stencil_wrmask, faceMask, writeMask);
- /* the front/back write masks must be updated together */
- cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
+ tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.dword = cmd->state.dynamic_stencil_wrmask));
}
void
uint32_t reference)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_STENCIL_REFERENCE, 2);
- if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
- cmd->state.dynamic.stencil_reference.front = reference;
- if (faceMask & VK_STENCIL_FACE_BACK_BIT)
- cmd->state.dynamic.stencil_reference.back = reference;
+ update_stencil_mask(&cmd->state.dynamic_stencil_ref, faceMask, reference);
- /* the front/back references must be updated together */
- cmd->state.dirty |= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
+ tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.dword = cmd->state.dynamic_stencil_ref));
}
void
const VkSampleLocationsInfoEXT* pSampleLocationsInfo)
{
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS, 9);
- tu6_emit_sample_locations(&cmd->draw_cs, pSampleLocationsInfo);
+ assert(pSampleLocationsInfo);
+
+ tu6_emit_sample_locations(&cs, pSampleLocationsInfo);
}
static void
{
enum tu_cmd_flush_bits flush_bits = 0;
+ if (src_mask & TU_ACCESS_HOST_WRITE) {
+ /* Host writes are always visible to CP, so only invalidate GPU caches */
+ cache->pending_flush_bits |= TU_CMD_FLAG_GPU_INVALIDATE;
+ }
+
if (src_mask & TU_ACCESS_SYSMEM_WRITE) {
+ /* Invalidate CP and 2D engine (make it do WFI + WFM if necessary) as
+ * well.
+ */
cache->pending_flush_bits |= TU_CMD_FLAG_ALL_INVALIDATE;
}
+ if (src_mask & TU_ACCESS_CP_WRITE) {
+ /* Flush the CP write queue. However a WFI shouldn't be necessary as
+ * WAIT_MEM_WRITES should cover it.
+ */
+ cache->pending_flush_bits |=
+ TU_CMD_FLAG_WAIT_MEM_WRITES |
+ TU_CMD_FLAG_GPU_INVALIDATE |
+ TU_CMD_FLAG_WAIT_FOR_ME;
+ }
+
#define SRC_FLUSH(domain, flush, invalidate) \
if (src_mask & TU_ACCESS_##domain##_WRITE) { \
cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
#undef SRC_INCOHERENT_FLUSH
- if (dst_mask & (TU_ACCESS_SYSMEM_READ | TU_ACCESS_SYSMEM_WRITE)) {
+ /* Treat host & sysmem write accesses the same, since the kernel implicitly
+ * drains the queue before signalling completion to the host.
+ */
+ if (dst_mask & (TU_ACCESS_SYSMEM_READ | TU_ACCESS_SYSMEM_WRITE |
+ TU_ACCESS_HOST_READ | TU_ACCESS_HOST_WRITE)) {
flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
}
#undef DST_INCOHERENT_FLUSH
if (dst_mask & TU_ACCESS_WFI_READ) {
- flush_bits |= TU_CMD_FLAG_WFI;
+ flush_bits |= cache->pending_flush_bits &
+ (TU_CMD_FLAG_ALL_FLUSH | TU_CMD_FLAG_WAIT_FOR_IDLE);
+ }
+
+ if (dst_mask & TU_ACCESS_WFM_READ) {
+ flush_bits |= cache->pending_flush_bits &
+ (TU_CMD_FLAG_ALL_FLUSH | TU_CMD_FLAG_WAIT_FOR_ME);
}
cache->flush_bits |= flush_bits;
enum tu_cmd_access_mask mask = 0;
/* If the GPU writes a buffer that is then read by an indirect draw
- * command, we theoretically need a WFI + WAIT_FOR_ME combination to
- * wait for the writes to complete. The WAIT_FOR_ME is performed as part
- * of the draw by the firmware, so we just need to execute a WFI.
+ * command, we theoretically need to emit a WFI to wait for any cache
+ * flushes, and then a WAIT_FOR_ME to wait on the CP for the WFI to
+ * complete. Waiting for the WFI to complete is performed as part of the
+ * draw by the firmware, so we just need to execute the WFI.
+ *
+ * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
+ * does CP_WAIT_FOR_ME, but we still need a WFI if the GPU writes it.
*/
if (flags &
(VK_ACCESS_INDIRECT_COMMAND_READ_BIT |
+ VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT |
VK_ACCESS_MEMORY_READ_BIT)) {
mask |= TU_ACCESS_WFI_READ;
}
if (flags &
(VK_ACCESS_INDIRECT_COMMAND_READ_BIT | /* Read performed by CP */
- VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT | /* Read performed by CP, I think */
VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT | /* Read performed by CP */
- VK_ACCESS_HOST_READ_BIT | /* sysmem by definition */
+ VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT | /* Read performed by CP */
VK_ACCESS_MEMORY_READ_BIT)) {
mask |= TU_ACCESS_SYSMEM_READ;
}
+ if (flags &
+ (VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT |
+ VK_ACCESS_MEMORY_WRITE_BIT)) {
+ mask |= TU_ACCESS_CP_WRITE;
+ }
+
+ if (flags &
+ (VK_ACCESS_HOST_READ_BIT |
+ VK_ACCESS_MEMORY_WRITE_BIT)) {
+ mask |= TU_ACCESS_HOST_READ;
+ }
+
if (flags &
(VK_ACCESS_HOST_WRITE_BIT |
- VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT | /* Write performed by CP, I think */
VK_ACCESS_MEMORY_WRITE_BIT)) {
- mask |= TU_ACCESS_SYSMEM_WRITE;
+ mask |= TU_ACCESS_HOST_WRITE;
}
if (flags &
cmd->record_result = result;
break;
}
+
+ if (secondary->has_tess)
+ cmd->has_tess = true;
} else {
assert(tu_cs_is_empty(&secondary->draw_cs));
assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
tu_cs_add_entries(&cmd->cs, &secondary->cs);
}
+
+ cmd->state.index_size = secondary->state.index_size; /* for restart index update */
}
cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
TU_FROM_HANDLE(tu_device, device, _device);
struct tu_cmd_pool *pool;
- pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
- VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
+ pool = vk_object_alloc(&device->vk, pAllocator, sizeof(*pool),
+ VK_OBJECT_TYPE_COMMAND_POOL);
if (pool == NULL)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
if (pAllocator)
pool->alloc = *pAllocator;
else
- pool->alloc = device->alloc;
+ pool->alloc = device->vk.alloc;
list_inithead(&pool->cmd_buffers);
list_inithead(&pool->free_cmd_buffers);
tu_cmd_buffer_destroy(cmd_buffer);
}
- vk_free2(&device->alloc, pAllocator, pool);
+ vk_object_free(&device->vk, pAllocator, pool);
}
VkResult
cmd->state.pass = pass;
cmd->state.subpass = pass->subpasses;
cmd->state.framebuffer = fb;
+ cmd->state.render_area = pRenderPassBegin->renderArea;
- tu_cmd_update_tiling_config(cmd, &pRenderPassBegin->renderArea);
tu_cmd_prepare_tile_store_ib(cmd);
/* Note: because this is external, any flushes will happen before draw_cs
cmd->state.cache.pending_flush_bits;
cmd->state.renderpass_cache.flush_bits = 0;
- tu_emit_load_clear(cmd, pRenderPassBegin);
+ tu_emit_renderpass_begin(cmd, pRenderPassBegin);
tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples);
tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
- /* note: use_hw_binning only checks tiling config */
- if (use_hw_binning(cmd))
- cmd->use_vsc_data = true;
+ tu_set_input_attachments(cmd, cmd->state.subpass);
for (uint32_t i = 0; i < fb->attachment_count; ++i) {
const struct tu_image_view *iview = fb->attachments[i].attachment;
tu_bo_list_add(&cmd->bo_list, iview->image->bo,
MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
}
+
+ cmd->state.dirty |= TU_CMD_DIRTY_DRAW_STATE;
}
void
tu6_emit_mrt(cmd, cmd->state.subpass, cs);
tu6_emit_msaa(cs, cmd->state.subpass->samples);
tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, false);
+
+ tu_set_input_attachments(cmd, cmd->state.subpass);
}
void
tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
}
-struct tu_draw_info
-{
- /**
- * Number of vertices.
- */
- uint32_t count;
-
- /**
- * Index of the first vertex.
- */
- int32_t vertex_offset;
-
- /**
- * First instance id.
- */
- uint32_t first_instance;
-
- /**
- * Number of instances.
- */
- uint32_t instance_count;
-
- /**
- * First index (indexed draws only).
- */
- uint32_t first_index;
-
- /**
- * Whether it's an indexed draw.
- */
- bool indexed;
-
- /**
- * Indirect draw parameters resource.
- */
- struct tu_buffer *indirect;
- uint64_t indirect_offset;
- uint32_t stride;
-
- /**
- * Draw count parameters resource.
- */
- struct tu_buffer *count_buffer;
- uint64_t count_buffer_offset;
-
- /**
- * Stream output parameters resource.
- */
- struct tu_buffer *streamout_buffer;
- uint64_t streamout_buffer_offset;
-};
-
-#define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
-#define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
-#define ENABLE_NON_GMEM (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_SYSMEM)
-
-enum tu_draw_state_group_id
-{
- TU_DRAW_STATE_PROGRAM,
- TU_DRAW_STATE_PROGRAM_BINNING,
- TU_DRAW_STATE_VB,
- TU_DRAW_STATE_VI,
- TU_DRAW_STATE_VI_BINNING,
- TU_DRAW_STATE_VP,
- TU_DRAW_STATE_RAST,
- TU_DRAW_STATE_DS,
- TU_DRAW_STATE_BLEND,
- TU_DRAW_STATE_VS_CONST,
- TU_DRAW_STATE_GS_CONST,
- TU_DRAW_STATE_FS_CONST,
- TU_DRAW_STATE_DESC_SETS,
- TU_DRAW_STATE_DESC_SETS_GMEM,
- TU_DRAW_STATE_DESC_SETS_LOAD,
- TU_DRAW_STATE_VS_PARAMS,
-
- TU_DRAW_STATE_COUNT,
-};
-
-struct tu_draw_state_group
-{
- enum tu_draw_state_group_id id;
- uint32_t enable_mask;
- struct tu_cs_entry ib;
-};
-
static void
tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
struct tu_descriptor_state *descriptors_state,
{
const struct tu_program_descriptor_linkage *link =
&pipeline->program.link[type];
- const struct ir3_ubo_analysis_state *state = &link->ubo_state;
+ const struct ir3_ubo_analysis_state *state = &link->const_state.ubo_state;
if (link->push_consts.count > 0) {
unsigned num_units = link->push_consts.count;
/* Dig out the descriptor from the descriptor state and read the VA from
* it.
*/
- assert(state->range[i].bindless);
- uint32_t *base = state->range[i].bindless_base == MAX_SETS ?
+ assert(state->range[i].ubo.bindless);
+ uint32_t *base = state->range[i].ubo.bindless_base == MAX_SETS ?
descriptors_state->dynamic_descriptors :
- descriptors_state->sets[state->range[i].bindless_base]->mapped_ptr;
- unsigned block = state->range[i].block;
- /* If the block in the shader here is in the dynamic descriptor set, it
- * is an index into the dynamic descriptor set which is combined from
- * dynamic descriptors and input attachments on-the-fly, and we don't
- * have access to it here. Instead we work backwards to get the index
- * into dynamic_descriptors.
- */
- if (state->range[i].bindless_base == MAX_SETS)
- block -= pipeline->layout->input_attachment_count;
+ descriptors_state->sets[state->range[i].ubo.bindless_base]->mapped_ptr;
+ unsigned block = state->range[i].ubo.block;
uint32_t *desc = base + block * A6XX_TEX_CONST_DWORDS;
uint64_t va = desc[0] | ((uint64_t)(desc[1] & A6XX_UBO_1_BASE_HI__MASK) << 32);
assert(va);
}
}
-static struct tu_cs_entry
+static struct tu_draw_state
tu6_emit_consts(struct tu_cmd_buffer *cmd,
const struct tu_pipeline *pipeline,
struct tu_descriptor_state *descriptors_state,
tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
- return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
-}
-
-static VkResult
-tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
- const struct tu_draw_info *draw,
- struct tu_cs_entry *entry)
-{
- /* TODO: fill out more than just base instance */
- const struct tu_program_descriptor_linkage *link =
- &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
- const struct ir3_const_state *const_state = &link->const_state;
- struct tu_cs cs;
-
- if (const_state->offsets.driver_param >= link->constlen) {
- *entry = (struct tu_cs_entry) {};
- return VK_SUCCESS;
- }
-
- VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
- if (result != VK_SUCCESS)
- return result;
-
- tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
- tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
- CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
- CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
- CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
- CP_LOAD_STATE6_0_NUM_UNIT(1));
- tu_cs_emit(&cs, 0);
- tu_cs_emit(&cs, 0);
-
- STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
-
- tu_cs_emit(&cs, 0);
- tu_cs_emit(&cs, 0);
- tu_cs_emit(&cs, draw->first_instance);
- tu_cs_emit(&cs, 0);
-
- *entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
- return VK_SUCCESS;
+ return tu_cs_end_draw_state(&cmd->sub_cs, &cs);
}
-static struct tu_cs_entry
+static struct tu_draw_state
tu6_emit_vertex_buffers(struct tu_cmd_buffer *cmd,
const struct tu_pipeline *pipeline)
{
cmd->vertex_bindings_set = pipeline->vi.bindings_used;
- return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
+ return tu_cs_end_draw_state(&cmd->sub_cs, &cs);
}
-static VkResult
-tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
- const struct tu_pipeline *pipeline,
- VkPipelineBindPoint bind_point,
- struct tu_cs_entry *entry,
- bool gmem)
+static uint64_t
+get_tess_param_bo_size(const struct tu_pipeline *pipeline,
+ uint32_t draw_count)
{
- struct tu_cs *draw_state = &cmd->sub_cs;
- struct tu_pipeline_layout *layout = pipeline->layout;
- struct tu_descriptor_state *descriptors_state =
- tu_get_descriptors_state(cmd, bind_point);
- const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
- const uint32_t *input_attachment_idx =
- pipeline->program.input_attachment_idx;
- uint32_t num_dynamic_descs = layout->dynamic_offset_count +
- layout->input_attachment_count;
- struct ts_cs_memory dynamic_desc_set;
- VkResult result;
-
- if (num_dynamic_descs > 0) {
- /* allocate and fill out dynamic descriptor set */
- result = tu_cs_alloc(draw_state, num_dynamic_descs,
- A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
- if (result != VK_SUCCESS)
- return result;
-
- memcpy(dynamic_desc_set.map, descriptors_state->input_attachments,
- layout->input_attachment_count * A6XX_TEX_CONST_DWORDS * 4);
+ /* TODO: For indirect draws, we can't compute the BO size ahead of time.
+ * Still not sure what to do here, so just allocate a reasonably large
+ * BO and hope for the best for now. */
+ if (!draw_count)
+ draw_count = 2048;
- if (gmem) {
- /* Patch input attachments to refer to GMEM instead */
- for (unsigned i = 0; i < layout->input_attachment_count; i++) {
- uint32_t *dst =
- &dynamic_desc_set.map[A6XX_TEX_CONST_DWORDS * i];
-
- /* The compiler has already laid out input_attachment_idx in the
- * final order of input attachments, so there's no need to go
- * through the pipeline layout finding input attachments.
- */
- unsigned attachment_idx = input_attachment_idx[i];
-
- /* It's possible for the pipeline layout to include an input
- * attachment which doesn't actually exist for the current
- * subpass. Of course, this is only valid so long as the pipeline
- * doesn't try to actually load that attachment. Just skip
- * patching in that scenario to avoid out-of-bounds accesses.
- */
- if (attachment_idx >= cmd->state.subpass->input_count)
- continue;
-
- uint32_t a = cmd->state.subpass->input_attachments[attachment_idx].attachment;
- const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
-
- assert(att->gmem_offset >= 0);
-
- dst[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
- dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
- dst[2] &= ~(A6XX_TEX_CONST_2_TYPE__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
- dst[2] |=
- A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
- A6XX_TEX_CONST_2_PITCH(tiling->tile0.extent.width * att->cpp);
- dst[3] = 0;
- dst[4] = cmd->device->physical_device->gmem_base + att->gmem_offset;
- dst[5] = A6XX_TEX_CONST_5_DEPTH(1);
- for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
- dst[i] = 0;
-
- if (cmd->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
- tu_finishme("patch input attachment pitch for secondary cmd buffer");
- }
- }
-
- memcpy(dynamic_desc_set.map + layout->input_attachment_count * A6XX_TEX_CONST_DWORDS,
- descriptors_state->dynamic_descriptors,
- layout->dynamic_offset_count * A6XX_TEX_CONST_DWORDS * 4);
- }
-
- uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg;
- uint32_t hlsq_update_value;
- switch (bind_point) {
- case VK_PIPELINE_BIND_POINT_GRAPHICS:
- sp_bindless_base_reg = REG_A6XX_SP_BINDLESS_BASE(0);
- hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
- hlsq_update_value = 0x7c000;
+ /* the tess param BO is pipeline->tess.param_stride bytes per patch,
+ * which includes both the per-vertex outputs and per-patch outputs
+ * build_primitive_map in ir3 calculates this stride
+ */
+ uint32_t verts_per_patch = pipeline->ia.primtype - DI_PT_PATCHES0;
+ uint32_t num_patches = draw_count / verts_per_patch;
+ return num_patches * pipeline->tess.param_stride;
+}
+
+static uint64_t
+get_tess_factor_bo_size(const struct tu_pipeline *pipeline,
+ uint32_t draw_count)
+{
+ /* TODO: For indirect draws, we can't compute the BO size ahead of time.
+ * Still not sure what to do here, so just allocate a reasonably large
+ * BO and hope for the best for now. */
+ if (!draw_count)
+ draw_count = 2048;
+
+ /* Each distinct patch gets its own tess factor output. */
+ uint32_t verts_per_patch = pipeline->ia.primtype - DI_PT_PATCHES0;
+ uint32_t num_patches = draw_count / verts_per_patch;
+ uint32_t factor_stride;
+ switch (pipeline->tess.patch_type) {
+ case IR3_TESS_ISOLINES:
+ factor_stride = 12;
break;
- case VK_PIPELINE_BIND_POINT_COMPUTE:
- sp_bindless_base_reg = REG_A6XX_SP_CS_BINDLESS_BASE(0);
- hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
- hlsq_update_value = 0x3e00;
+ case IR3_TESS_TRIANGLES:
+ factor_stride = 20;
+ break;
+ case IR3_TESS_QUADS:
+ factor_stride = 28;
break;
default:
- unreachable("bad bind point");
- }
-
- /* Be careful here to *not* refer to the pipeline, so that if only the
- * pipeline changes we don't have to emit this again (except if there are
- * dynamic descriptors in the pipeline layout). This means always emitting
- * all the valid descriptors, which means that we always have to put the
- * dynamic descriptor in the driver-only slot at the end
- */
- uint32_t num_user_sets = util_last_bit(descriptors_state->valid);
- uint32_t num_sets = num_user_sets;
- if (num_dynamic_descs > 0) {
- num_user_sets = MAX_SETS;
- num_sets = num_user_sets + 1;
+ unreachable("bad tessmode");
}
+ return factor_stride * num_patches;
+}
- unsigned regs[2] = { sp_bindless_base_reg, hlsq_bindless_base_reg };
-
+static VkResult
+tu6_emit_tess_consts(struct tu_cmd_buffer *cmd,
+ uint32_t draw_count,
+ const struct tu_pipeline *pipeline,
+ struct tu_draw_state *state,
+ uint64_t *factor_iova)
+{
struct tu_cs cs;
- result = tu_cs_begin_sub_stream(draw_state, ARRAY_SIZE(regs) * (1 + num_sets * 2) + 2, &cs);
+ VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 16, &cs);
if (result != VK_SUCCESS)
return result;
- if (num_sets > 0) {
- for (unsigned i = 0; i < ARRAY_SIZE(regs); i++) {
- tu_cs_emit_pkt4(&cs, regs[i], num_sets * 2);
- for (unsigned j = 0; j < num_user_sets; j++) {
- if (descriptors_state->valid & (1 << j)) {
- /* magic | 3 copied from the blob */
- tu_cs_emit_qw(&cs, descriptors_state->sets[j]->va | 3);
- } else {
- tu_cs_emit_qw(&cs, 0 | 3);
- }
- }
- if (num_dynamic_descs > 0) {
- tu_cs_emit_qw(&cs, dynamic_desc_set.iova | 3);
- }
- }
-
- tu_cs_emit_regs(&cs, A6XX_HLSQ_UPDATE_CNTL(hlsq_update_value));
- }
-
- *entry = tu_cs_end_sub_stream(draw_state, &cs);
- return VK_SUCCESS;
-}
-
-static void
-tu6_emit_streamout(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
-{
- struct tu_streamout_state *tf = &cmd->state.pipeline->streamout;
-
- for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
- struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
- if (!buf)
- continue;
-
- uint32_t offset;
- offset = cmd->state.streamout_buf.offsets[i];
+ uint64_t tess_factor_size = get_tess_factor_bo_size(pipeline, draw_count);
+ uint64_t tess_param_size = get_tess_param_bo_size(pipeline, draw_count);
+ uint64_t tess_bo_size = tess_factor_size + tess_param_size;
+ if (tess_bo_size > 0) {
+ struct tu_bo *tess_bo;
+ result = tu_get_scratch_bo(cmd->device, tess_bo_size, &tess_bo);
+ if (result != VK_SUCCESS)
+ return result;
- tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_BASE(i, .bo = buf->bo,
- .bo_offset = buf->bo_offset));
- tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_SIZE(i, buf->size));
+ tu_bo_list_add(&cmd->bo_list, tess_bo,
+ MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
+ uint64_t tess_factor_iova = tess_bo->iova;
+ uint64_t tess_param_iova = tess_factor_iova + tess_factor_size;
- if (cmd->state.streamout_reset & (1 << i)) {
- tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, offset));
- cmd->state.streamout_reset &= ~(1 << i);
- } else {
- tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
- tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
- CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
- CP_MEM_TO_REG_0_CNT(0));
- tu_cs_emit_qw(cs, cmd->scratch_bo.iova +
- ctrl_offset(flush_base[i].offset));
- }
+ tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
+ tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(pipeline->tess.hs_bo_regid) |
+ CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
+ CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER) |
+ CP_LOAD_STATE6_0_NUM_UNIT(1));
+ tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
+ tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
+ tu_cs_emit_qw(&cs, tess_param_iova);
+ tu_cs_emit_qw(&cs, tess_factor_iova);
+
+ tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
+ tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(pipeline->tess.ds_bo_regid) |
+ CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
+ CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER) |
+ CP_LOAD_STATE6_0_NUM_UNIT(1));
+ tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
+ tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
+ tu_cs_emit_qw(&cs, tess_param_iova);
+ tu_cs_emit_qw(&cs, tess_factor_iova);
- tu_cs_emit_regs(cs, A6XX_VPC_SO_FLUSH_BASE(i, .bo = &cmd->scratch_bo,
- .bo_offset =
- ctrl_offset(flush_base[i])));
- }
-
- if (cmd->state.streamout_enabled) {
- tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + (2 * tf->prog_count));
- tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
- tu_cs_emit(cs, tf->vpc_so_buf_cntl);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(0));
- tu_cs_emit(cs, tf->ncomp[0]);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(1));
- tu_cs_emit(cs, tf->ncomp[1]);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(2));
- tu_cs_emit(cs, tf->ncomp[2]);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(3));
- tu_cs_emit(cs, tf->ncomp[3]);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
- tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
- for (unsigned i = 0; i < tf->prog_count; i++) {
- tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
- tu_cs_emit(cs, tf->prog[i]);
- }
- } else {
- tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
- tu_cs_emit(cs, 0);
- tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
- tu_cs_emit(cs, 0);
+ *factor_iova = tess_factor_iova;
}
+ *state = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
+ return VK_SUCCESS;
}
static VkResult
-tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- const struct tu_draw_info *draw)
+tu6_draw_common(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ bool indexed,
+ /* note: draw_count is 0 for indirect */
+ uint32_t draw_count)
{
const struct tu_pipeline *pipeline = cmd->state.pipeline;
- const struct tu_dynamic_state *dynamic = &cmd->state.dynamic;
- struct tu_draw_state_group draw_state_groups[TU_DRAW_STATE_COUNT];
- uint32_t draw_state_group_count = 0;
VkResult result;
struct tu_descriptor_state *descriptors_state =
&cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
- /* TODO lrz */
-
- tu_cs_emit_regs(cs,
- A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart =
- pipeline->ia.primitive_restart && draw->indexed));
-
- if (cmd->state.dirty &
- (TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH) &&
- (pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH)) {
- tu6_emit_gras_su_cntl(cs, pipeline->rast.gras_su_cntl,
- dynamic->line_width);
- }
-
- if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) &&
- (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
- tu6_emit_stencil_compare_mask(cs, dynamic->stencil_compare_mask.front,
- dynamic->stencil_compare_mask.back);
- }
-
- if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) &&
- (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
- tu6_emit_stencil_write_mask(cs, dynamic->stencil_write_mask.front,
- dynamic->stencil_write_mask.back);
- }
-
- if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) &&
- (pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
- tu6_emit_stencil_reference(cs, dynamic->stencil_reference.front,
- dynamic->stencil_reference.back);
- }
-
- if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
- (pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
- tu6_emit_viewport(cs, &cmd->state.dynamic.viewport.viewports[0]);
- }
+ tu_emit_cache_flush_renderpass(cmd, cs);
- if ((cmd->state.dirty & TU_CMD_DIRTY_DYNAMIC_SCISSOR) &&
- (pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
- tu6_emit_scissor(cs, &cmd->state.dynamic.scissor.scissors[0]);
- }
+ /* TODO lrz */
- if (cmd->state.dirty & TU_CMD_DIRTY_PIPELINE) {
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_PROGRAM,
- .enable_mask = ENABLE_DRAW,
- .ib = pipeline->program.state_ib,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_PROGRAM_BINNING,
- .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
- .ib = pipeline->program.binning_state_ib,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_VI,
- .enable_mask = ENABLE_DRAW,
- .ib = pipeline->vi.state_ib,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_VI_BINNING,
- .enable_mask = CP_SET_DRAW_STATE__0_BINNING,
- .ib = pipeline->vi.binning_state_ib,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_VP,
- .enable_mask = ENABLE_ALL,
- .ib = pipeline->vp.state_ib,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_RAST,
- .enable_mask = ENABLE_ALL,
- .ib = pipeline->rast.state_ib,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_DS,
- .enable_mask = ENABLE_ALL,
- .ib = pipeline->ds.state_ib,
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_BLEND,
- .enable_mask = ENABLE_ALL,
- .ib = pipeline->blend.state_ib,
- };
- }
+ tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(
+ .primitive_restart =
+ pipeline->ia.primitive_restart && indexed,
+ .tess_upper_left_domain_origin =
+ pipeline->tess.upper_left_domain_origin));
if (cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) {
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_VS_CONST,
- .enable_mask = ENABLE_ALL,
- .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_GS_CONST,
- .enable_mask = ENABLE_ALL,
- .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_GEOMETRY)
- };
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_FS_CONST,
- .enable_mask = ENABLE_DRAW,
- .ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
- };
- }
-
- if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) {
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_VB,
- .enable_mask = ENABLE_ALL,
- .ib = tu6_emit_vertex_buffers(cmd, pipeline)
- };
- }
-
- if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS)
- tu6_emit_streamout(cmd, cs);
-
- /* If there are any any dynamic descriptors, then we may need to re-emit
- * them after every pipeline change in case the number of input attachments
- * changes. We also always need to re-emit after a pipeline change if there
- * are any input attachments, because the input attachment index comes from
- * the pipeline. Finally, it can also happen that the subpass changes
- * without the pipeline changing, in which case the GMEM descriptors need
- * to be patched differently.
- *
- * TODO: We could probably be clever and avoid re-emitting state on
- * pipeline changes if the number of input attachments is always 0. We
- * could also only re-emit dynamic state.
- */
- if (cmd->state.dirty & TU_CMD_DIRTY_DESCRIPTOR_SETS) {
- struct tu_cs_entry desc_sets, desc_sets_gmem;
- bool need_gmem_desc_set = pipeline->layout->input_attachment_count > 0;
-
- result = tu6_emit_descriptor_sets(cmd, pipeline,
- VK_PIPELINE_BIND_POINT_GRAPHICS,
- &desc_sets, false);
+ cmd->state.shader_const[MESA_SHADER_VERTEX] =
+ tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX);
+ cmd->state.shader_const[MESA_SHADER_TESS_CTRL] =
+ tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_TESS_CTRL);
+ cmd->state.shader_const[MESA_SHADER_TESS_EVAL] =
+ tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_TESS_EVAL);
+ cmd->state.shader_const[MESA_SHADER_GEOMETRY] =
+ tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_GEOMETRY);
+ cmd->state.shader_const[MESA_SHADER_FRAGMENT] =
+ tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT);
+ }
+
+ if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
+ cmd->state.vertex_buffers = tu6_emit_vertex_buffers(cmd, pipeline);
+
+ bool has_tess =
+ pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
+ struct tu_draw_state tess_consts = {};
+ if (has_tess) {
+ uint64_t tess_factor_iova = 0;
+
+ cmd->has_tess = true;
+ result = tu6_emit_tess_consts(cmd, draw_count, pipeline, &tess_consts, &tess_factor_iova);
if (result != VK_SUCCESS)
return result;
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_DESC_SETS,
- .enable_mask = need_gmem_desc_set ? ENABLE_NON_GMEM : ENABLE_ALL,
- .ib = desc_sets,
- };
-
- if (need_gmem_desc_set) {
- result = tu6_emit_descriptor_sets(cmd, pipeline,
- VK_PIPELINE_BIND_POINT_GRAPHICS,
- &desc_sets_gmem, true);
- if (result != VK_SUCCESS)
- return result;
-
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_DESC_SETS_GMEM,
- .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
- .ib = desc_sets_gmem,
- };
- }
-
- /* We need to reload the descriptors every time the descriptor sets
- * change. However, the commands we send only depend on the pipeline
- * because the whole point is to cache descriptors which are used by the
- * pipeline. There's a problem here, in that the firmware has an
- * "optimization" which skips executing groups that are set to the same
- * value as the last draw. This means that if the descriptor sets change
- * but not the pipeline, we'd try to re-execute the same buffer which
- * the firmware would ignore and we wouldn't pre-load the new
- * descriptors. The blob seems to re-emit the LOAD_STATE group whenever
- * the descriptor sets change, which we emulate here by copying the
- * pre-prepared buffer.
+ /* this sequence matches what the blob does before every tess draw
+ * PC_TESSFACTOR_ADDR_LO is a non-context register and needs a wfi
+ * before writing to it
*/
- const struct tu_cs_entry *load_entry = &pipeline->load_state.state_ib;
- if (load_entry->size > 0) {
- struct tu_cs load_cs;
- result = tu_cs_begin_sub_stream(&cmd->sub_cs, load_entry->size, &load_cs);
- if (result != VK_SUCCESS)
- return result;
- tu_cs_emit_array(&load_cs,
- (uint32_t *)((char *)load_entry->bo->map + load_entry->offset),
- load_entry->size / 4);
- struct tu_cs_entry load_copy = tu_cs_end_sub_stream(&cmd->sub_cs, &load_cs);
-
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_DESC_SETS_LOAD,
- /* The blob seems to not enable this for binning, even when
- * resources would actually be used in the binning shader.
- * Presumably the overhead of prefetching the resources isn't
- * worth it.
- */
- .enable_mask = ENABLE_DRAW,
- .ib = load_copy,
- };
- }
- }
+ tu_cs_emit_wfi(cs);
- struct tu_cs_entry vs_params;
- result = tu6_emit_vs_params(cmd, draw, &vs_params);
- if (result != VK_SUCCESS)
- return result;
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
+ tu_cs_emit_qw(cs, tess_factor_iova);
- draw_state_groups[draw_state_group_count++] =
- (struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_VS_PARAMS,
- .enable_mask = ENABLE_ALL,
- .ib = vs_params,
- };
+ tu_cs_emit_pkt7(cs, CP_SET_SUBDRAW_SIZE, 1);
+ tu_cs_emit(cs, draw_count);
+ }
- tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_group_count);
- for (uint32_t i = 0; i < draw_state_group_count; i++) {
- const struct tu_draw_state_group *group = &draw_state_groups[i];
- debug_assert((group->enable_mask & ~ENABLE_ALL) == 0);
- uint32_t cp_set_draw_state =
- CP_SET_DRAW_STATE__0_COUNT(group->ib.size / 4) |
- group->enable_mask |
- CP_SET_DRAW_STATE__0_GROUP_ID(group->id);
- uint64_t iova;
- if (group->ib.size) {
- iova = group->ib.bo->iova + group->ib.offset;
- } else {
- cp_set_draw_state |= CP_SET_DRAW_STATE__0_DISABLE;
- iova = 0;
+ /* for the first draw in a renderpass, re-emit all the draw states
+ *
+ * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
+ * used, then draw states must be re-emitted. note however this only happens
+ * in the sysmem path, so this can be skipped this for the gmem path (TODO)
+ *
+ * the two input attachment states are excluded because secondary command
+ * buffer doesn't have a state ib to restore it, and not re-emitting them
+ * is OK since CmdClearAttachments won't disable/overwrite them
+ */
+ if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE) {
+ tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (TU_DRAW_STATE_COUNT - 2));
+
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_TESS, tess_consts);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS, pipeline->ds_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_CONST, cmd->state.shader_const[MESA_SHADER_VERTEX]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_HS_CONST, cmd->state.shader_const[MESA_SHADER_TESS_CTRL]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS_CONST, cmd->state.shader_const[MESA_SHADER_TESS_EVAL]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS_CONST, cmd->state.shader_const[MESA_SHADER_GEOMETRY]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_CONST, cmd->state.shader_const[MESA_SHADER_FRAGMENT]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
+
+ for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) {
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
+ ((pipeline->dynamic_state_mask & BIT(i)) ?
+ cmd->state.dynamic_state[i] :
+ pipeline->dynamic_state[i]));
}
+ } else {
- tu_cs_emit(cs, cp_set_draw_state);
- tu_cs_emit_qw(cs, iova);
+ /* emit draw states that were just updated
+ * note we eventually don't want to have to emit anything here
+ */
+ uint32_t draw_state_count =
+ has_tess +
+ ((cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) ? 5 : 0) +
+ ((cmd->state.dirty & TU_CMD_DIRTY_DESC_SETS_LOAD) ? 1 : 0) +
+ ((cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) ? 1 : 0) +
+ 1; /* vs_params */
+
+ tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_count);
+
+ /* We may need to re-emit tess consts if the current draw call is
+ * sufficiently larger than the last draw call. */
+ if (has_tess)
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_TESS, tess_consts);
+ if (cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) {
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_CONST, cmd->state.shader_const[MESA_SHADER_VERTEX]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_HS_CONST, cmd->state.shader_const[MESA_SHADER_TESS_CTRL]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS_CONST, cmd->state.shader_const[MESA_SHADER_TESS_EVAL]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS_CONST, cmd->state.shader_const[MESA_SHADER_GEOMETRY]);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_CONST, cmd->state.shader_const[MESA_SHADER_FRAGMENT]);
+ }
+ if (cmd->state.dirty & TU_CMD_DIRTY_DESC_SETS_LOAD)
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, pipeline->load_state);
+ if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
+ tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
}
tu_cs_sanity_check(cs);
- /* track BOs */
- if (cmd->state.dirty & TU_CMD_DIRTY_STREAMOUT_BUFFERS) {
- for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
- const struct tu_buffer *buf = cmd->state.streamout_buf.buffers[i];
- if (buf) {
- tu_bo_list_add(&cmd->bo_list, buf->bo,
- MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE);
- }
- }
- }
-
/* There are too many graphics dirty bits to list here, so just list the
* bits to preserve instead. The only things not emitted here are
* compute-related state.
*/
- cmd->state.dirty &= (TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS | TU_CMD_DIRTY_COMPUTE_PIPELINE);
+ cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
return VK_SUCCESS;
}
-static void
-tu6_emit_draw_indirect(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- const struct tu_draw_info *draw)
+static uint32_t
+tu_draw_initiator(struct tu_cmd_buffer *cmd, enum pc_di_src_sel src_sel)
{
- const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
- bool has_gs = cmd->state.pipeline->active_stages &
- VK_SHADER_STAGE_GEOMETRY_BIT;
-
- tu_cs_emit_regs(cs,
- A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
- A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
-
- if (draw->indexed) {
- const enum a4xx_index_size index_size =
- tu6_index_size(cmd->state.index_type);
- const uint32_t index_bytes =
- (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
- const struct tu_buffer *index_buf = cmd->state.index_buffer;
- unsigned max_indicies =
- (index_buf->size - cmd->state.index_offset) / index_bytes;
-
- const uint32_t cp_draw_indx =
- CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
- CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
- CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
- CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
- COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
-
- tu_cs_emit_pkt7(cs, CP_DRAW_INDX_INDIRECT, 6);
- tu_cs_emit(cs, cp_draw_indx);
- tu_cs_emit_qw(cs, index_buf->bo->iova + cmd->state.index_offset);
- tu_cs_emit(cs, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
- tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
- } else {
- const uint32_t cp_draw_indx =
- CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
- CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
- CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
- COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
-
- tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT, 3);
- tu_cs_emit(cs, cp_draw_indx);
- tu_cs_emit_qw(cs, draw->indirect->bo->iova + draw->indirect_offset);
+ const struct tu_pipeline *pipeline = cmd->state.pipeline;
+ uint32_t initiator =
+ CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(pipeline->ia.primtype) |
+ CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel) |
+ CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd->state.index_size) |
+ CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY);
+
+ if (pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT)
+ initiator |= CP_DRAW_INDX_OFFSET_0_GS_ENABLE;
+
+ switch (pipeline->tess.patch_type) {
+ case IR3_TESS_TRIANGLES:
+ initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES) |
+ CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
+ break;
+ case IR3_TESS_ISOLINES:
+ initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES) |
+ CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
+ break;
+ case IR3_TESS_NONE:
+ initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS);
+ break;
+ case IR3_TESS_QUADS:
+ initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS) |
+ CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
+ break;
}
-
- tu_bo_list_add(&cmd->bo_list, draw->indirect->bo, MSM_SUBMIT_BO_READ);
+ return initiator;
}
-static void
-tu6_emit_draw_direct(struct tu_cmd_buffer *cmd,
- struct tu_cs *cs,
- const struct tu_draw_info *draw)
+
+static uint32_t
+vs_params_offset(struct tu_cmd_buffer *cmd)
{
+ const struct tu_program_descriptor_linkage *link =
+ &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
+ const struct ir3_const_state *const_state = &link->const_state;
- const enum pc_di_primtype primtype = cmd->state.pipeline->ia.primtype;
- bool has_gs = cmd->state.pipeline->active_stages &
- VK_SHADER_STAGE_GEOMETRY_BIT;
+ if (const_state->offsets.driver_param >= link->constlen)
+ return 0;
- tu_cs_emit_regs(cs,
- A6XX_VFD_INDEX_OFFSET(draw->vertex_offset),
- A6XX_VFD_INSTANCE_START_OFFSET(draw->first_instance));
-
- /* TODO hw binning */
- if (draw->indexed) {
- const enum a4xx_index_size index_size =
- tu6_index_size(cmd->state.index_type);
- const uint32_t index_bytes =
- (cmd->state.index_type == VK_INDEX_TYPE_UINT32) ? 4 : 2;
- const struct tu_buffer *buf = cmd->state.index_buffer;
- const VkDeviceSize offset = buf->bo_offset + cmd->state.index_offset +
- index_bytes * draw->first_index;
- const uint32_t size = index_bytes * draw->count;
-
- const uint32_t cp_draw_indx =
- CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
- CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
- CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
- CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
- COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
-
- tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
- tu_cs_emit(cs, cp_draw_indx);
- tu_cs_emit(cs, draw->instance_count);
- tu_cs_emit(cs, draw->count);
- tu_cs_emit(cs, 0x0); /* XXX */
- tu_cs_emit_qw(cs, buf->bo->iova + offset);
- tu_cs_emit(cs, size);
- } else {
- const uint32_t cp_draw_indx =
- CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
- CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
- CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY) |
- COND(has_gs, CP_DRAW_INDX_OFFSET_0_GS_ENABLE) | 0x2000;
-
- tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
- tu_cs_emit(cs, cp_draw_indx);
- tu_cs_emit(cs, draw->instance_count);
- tu_cs_emit(cs, draw->count);
- }
+ /* this layout is required by CP_DRAW_INDIRECT_MULTI */
+ STATIC_ASSERT(IR3_DP_DRAWID == 0);
+ STATIC_ASSERT(IR3_DP_VTXID_BASE == 1);
+ STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
+
+ /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
+ assert(const_state->offsets.driver_param != 0);
+
+ return const_state->offsets.driver_param;
}
-static void
-tu_draw(struct tu_cmd_buffer *cmd, const struct tu_draw_info *draw)
+static struct tu_draw_state
+tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
+ uint32_t vertex_offset,
+ uint32_t first_instance)
{
- struct tu_cs *cs = &cmd->draw_cs;
- VkResult result;
-
- tu_emit_cache_flush_renderpass(cmd, cs);
+ uint32_t offset = vs_params_offset(cmd);
- result = tu6_bind_draw_states(cmd, cs, draw);
+ struct tu_cs cs;
+ VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 3 + (offset ? 8 : 0), &cs);
if (result != VK_SUCCESS) {
cmd->record_result = result;
- return;
+ return (struct tu_draw_state) {};
}
- if (draw->indirect)
- tu6_emit_draw_indirect(cmd, cs, draw);
- else
- tu6_emit_draw_direct(cmd, cs, draw);
+ /* TODO: don't make a new draw state when it doesn't change */
- if (cmd->state.streamout_enabled) {
- for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
- if (cmd->state.streamout_enabled & (1 << i))
- tu6_emit_event_write(cmd, cs, FLUSH_SO_0 + i);
- }
+ tu_cs_emit_regs(&cs,
+ A6XX_VFD_INDEX_OFFSET(vertex_offset),
+ A6XX_VFD_INSTANCE_START_OFFSET(first_instance));
+
+ if (offset) {
+ tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
+ tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
+ CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
+ CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
+ CP_LOAD_STATE6_0_NUM_UNIT(1));
+ tu_cs_emit(&cs, 0);
+ tu_cs_emit(&cs, 0);
+
+ tu_cs_emit(&cs, 0);
+ tu_cs_emit(&cs, vertex_offset);
+ tu_cs_emit(&cs, first_instance);
+ tu_cs_emit(&cs, 0);
}
- tu_cs_sanity_check(cs);
+ struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
+ return (struct tu_draw_state) {entry.bo->iova + entry.offset, entry.size / 4};
}
void
uint32_t firstVertex,
uint32_t firstInstance)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
- struct tu_draw_info info = {};
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs *cs = &cmd->draw_cs;
+
+ cmd->state.vs_params = tu6_emit_vs_params(cmd, firstVertex, firstInstance);
- info.count = vertexCount;
- info.instance_count = instanceCount;
- info.first_instance = firstInstance;
- info.vertex_offset = firstVertex;
+ tu6_draw_common(cmd, cs, false, vertexCount);
- tu_draw(cmd_buffer, &info);
+ tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
+ tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
+ tu_cs_emit(cs, instanceCount);
+ tu_cs_emit(cs, vertexCount);
}
void
int32_t vertexOffset,
uint32_t firstInstance)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
- struct tu_draw_info info = {};
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ struct tu_cs *cs = &cmd->draw_cs;
- info.indexed = true;
- info.count = indexCount;
- info.instance_count = instanceCount;
- info.first_index = firstIndex;
- info.vertex_offset = vertexOffset;
- info.first_instance = firstInstance;
+ cmd->state.vs_params = tu6_emit_vs_params(cmd, vertexOffset, firstInstance);
- tu_draw(cmd_buffer, &info);
+ tu6_draw_common(cmd, cs, true, indexCount);
+
+ tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
+ tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
+ tu_cs_emit(cs, instanceCount);
+ tu_cs_emit(cs, indexCount);
+ tu_cs_emit(cs, firstIndex);
+ tu_cs_emit_qw(cs, cmd->state.index_va);
+ tu_cs_emit(cs, cmd->state.max_index_count);
+}
+
+/* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
+ * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
+ * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
+ * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
+ * before draw opcodes that don't need it.
+ */
+static void
+draw_wfm(struct tu_cmd_buffer *cmd)
+{
+ cmd->state.renderpass_cache.flush_bits |=
+ cmd->state.renderpass_cache.pending_flush_bits & TU_CMD_FLAG_WAIT_FOR_ME;
+ cmd->state.renderpass_cache.pending_flush_bits &= ~TU_CMD_FLAG_WAIT_FOR_ME;
}
void
uint32_t drawCount,
uint32_t stride)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
- TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
- struct tu_draw_info info = {};
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ TU_FROM_HANDLE(tu_buffer, buf, _buffer);
+ struct tu_cs *cs = &cmd->draw_cs;
- info.count = drawCount;
- info.indirect = buffer;
- info.indirect_offset = offset;
- info.stride = stride;
+ cmd->state.vs_params = (struct tu_draw_state) {};
+
+ /* The latest known a630_sqe.fw fails to wait for WFI before reading the
+ * indirect buffer when using CP_DRAW_INDIRECT_MULTI, so we have to fall
+ * back to CP_WAIT_FOR_ME except for a650 which has a fixed firmware.
+ *
+ * TODO: There may be newer a630_sqe.fw released in the future which fixes
+ * this, if so we should detect it and avoid this workaround.
+ */
+ if (cmd->device->physical_device->gpu_id != 650)
+ draw_wfm(cmd);
- tu_draw(cmd_buffer, &info);
+ tu6_draw_common(cmd, cs, false, 0);
+
+ tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 6);
+ tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
+ tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL) |
+ A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
+ tu_cs_emit(cs, drawCount);
+ tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
+ tu_cs_emit(cs, stride);
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
}
void
uint32_t drawCount,
uint32_t stride)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
- TU_FROM_HANDLE(tu_buffer, buffer, _buffer);
- struct tu_draw_info info = {};
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ TU_FROM_HANDLE(tu_buffer, buf, _buffer);
+ struct tu_cs *cs = &cmd->draw_cs;
- info.indexed = true;
- info.count = drawCount;
- info.indirect = buffer;
- info.indirect_offset = offset;
- info.stride = stride;
+ cmd->state.vs_params = (struct tu_draw_state) {};
+
+ if (cmd->device->physical_device->gpu_id != 650)
+ draw_wfm(cmd);
+
+ tu6_draw_common(cmd, cs, true, 0);
+
+ tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 9);
+ tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
+ tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED) |
+ A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
+ tu_cs_emit(cs, drawCount);
+ tu_cs_emit_qw(cs, cmd->state.index_va);
+ tu_cs_emit(cs, cmd->state.max_index_count);
+ tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
+ tu_cs_emit(cs, stride);
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
+}
+
+void
+tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer,
+ VkBuffer _buffer,
+ VkDeviceSize offset,
+ VkBuffer countBuffer,
+ VkDeviceSize countBufferOffset,
+ uint32_t drawCount,
+ uint32_t stride)
+{
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ TU_FROM_HANDLE(tu_buffer, buf, _buffer);
+ TU_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
+ struct tu_cs *cs = &cmd->draw_cs;
+
+ cmd->state.vs_params = (struct tu_draw_state) {};
+
+ /* It turns out that the firmware we have for a650 only partially fixed the
+ * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
+ * before reading indirect parameters. It waits for WFI's before reading
+ * the draw parameters, but after reading the indirect count :(.
+ */
+ draw_wfm(cmd);
+
+ tu6_draw_common(cmd, cs, false, 0);
+
+ tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 8);
+ tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
+ tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT) |
+ A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
+ tu_cs_emit(cs, drawCount);
+ tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
+ tu_cs_emit_qw(cs, count_buf->bo->iova + count_buf->bo_offset + countBufferOffset);
+ tu_cs_emit(cs, stride);
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
+ tu_bo_list_add(&cmd->bo_list, count_buf->bo, MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
+}
- tu_draw(cmd_buffer, &info);
+void
+tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer,
+ VkBuffer _buffer,
+ VkDeviceSize offset,
+ VkBuffer countBuffer,
+ VkDeviceSize countBufferOffset,
+ uint32_t drawCount,
+ uint32_t stride)
+{
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ TU_FROM_HANDLE(tu_buffer, buf, _buffer);
+ TU_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
+ struct tu_cs *cs = &cmd->draw_cs;
+
+ cmd->state.vs_params = (struct tu_draw_state) {};
+
+ draw_wfm(cmd);
+
+ tu6_draw_common(cmd, cs, true, 0);
+
+ tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 11);
+ tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
+ tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED) |
+ A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
+ tu_cs_emit(cs, drawCount);
+ tu_cs_emit_qw(cs, cmd->state.index_va);
+ tu_cs_emit(cs, cmd->state.max_index_count);
+ tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
+ tu_cs_emit_qw(cs, count_buf->bo->iova + count_buf->bo_offset + countBufferOffset);
+ tu_cs_emit(cs, stride);
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
+ tu_bo_list_add(&cmd->bo_list, count_buf->bo, MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_DUMP);
}
void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
uint32_t counterOffset,
uint32_t vertexStride)
{
- TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
- TU_FROM_HANDLE(tu_buffer, buffer, _counterBuffer);
+ TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
+ TU_FROM_HANDLE(tu_buffer, buf, _counterBuffer);
+ struct tu_cs *cs = &cmd->draw_cs;
- struct tu_draw_info info = {};
+ /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
+ * Plus, for the common case where the counter buffer is written by
+ * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
+ * complete which means we need a WAIT_FOR_ME anyway.
+ */
+ draw_wfm(cmd);
- info.instance_count = instanceCount;
- info.first_instance = firstInstance;
- info.streamout_buffer = buffer;
- info.streamout_buffer_offset = counterBufferOffset;
- info.stride = vertexStride;
+ cmd->state.vs_params = tu6_emit_vs_params(cmd, 0, firstInstance);
- tu_draw(cmd_buffer, &info);
+ tu6_draw_common(cmd, cs, false, 0);
+
+ tu_cs_emit_pkt7(cs, CP_DRAW_AUTO, 6);
+ tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_XFB));
+ tu_cs_emit(cs, instanceCount);
+ tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + counterBufferOffset);
+ tu_cs_emit(cs, counterOffset);
+ tu_cs_emit(cs, vertexStride);
+
+ tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
}
struct tu_dispatch_info
struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
struct tu_descriptor_state *descriptors_state =
&cmd->descriptors[VK_PIPELINE_BIND_POINT_COMPUTE];
- VkResult result;
/* TODO: We could probably flush less if we add a compute_flush_bits
* bitfield.
*/
tu_emit_cache_flush(cmd, cs);
- if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_PIPELINE)
- tu_cs_emit_ib(cs, &pipeline->program.state_ib);
-
- struct tu_cs_entry ib;
-
- ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE);
- if (ib.size)
- tu_cs_emit_ib(cs, &ib);
+ /* note: no reason to have this in a separate IB */
+ tu_cs_emit_state_ib(cs,
+ tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_COMPUTE));
tu_emit_compute_driver_params(cs, pipeline, info);
- if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS) {
- result = tu6_emit_descriptor_sets(cmd, pipeline,
- VK_PIPELINE_BIND_POINT_COMPUTE, &ib,
- false);
- if (result != VK_SUCCESS) {
- cmd->record_result = result;
- return;
- }
- }
-
- if (ib.size)
- tu_cs_emit_ib(cs, &ib);
-
- if ((cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS) &&
- pipeline->load_state.state_ib.size > 0) {
- tu_cs_emit_ib(cs, &pipeline->load_state.state_ib);
- }
+ if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD)
+ tu_cs_emit_state_ib(cs, pipeline->load_state);
- cmd->state.dirty &=
- ~(TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS | TU_CMD_DIRTY_COMPUTE_PIPELINE);
+ cmd->state.dirty &= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
projects / mesa.git / blobdiff