freedreno/ir3: move ubo_state into const_state
[mesa.git] / src / freedreno / vulkan / tu_private.h
index 527bf817bbc927a348dae73fdec5614774a5ea41..39f303ee7d7c596787bcc169316a161e9e094a9a 100644 (file)
@@ -62,6 +62,7 @@
 
 #include "tu_descriptor_set.h"
 #include "tu_extensions.h"
+#include "tu_util.h"
 
 /* Pre-declarations needed for WSI entrypoints */
 struct wl_surface;
@@ -129,6 +130,7 @@ tu_minify(uint32_t n, uint32_t levels)
    })
 
 #define COND(bool, val) ((bool) ? (val) : 0)
+#define BIT(bit) (1u << (bit))
 
 /* Whenever we generate an error, pass it through this function. Useful for
  * debugging, where we can break on it. Only call at error site, not when
@@ -409,6 +411,42 @@ struct ts_cs_memory {
    uint64_t iova;
 };
 
+struct tu_draw_state {
+   uint64_t iova : 48;
+   uint32_t size : 16;
+};
+
+enum tu_dynamic_state
+{
+   /* re-use VK_DYNAMIC_STATE_ enums for non-extended dynamic states */
+   TU_DYNAMIC_STATE_SAMPLE_LOCATIONS = VK_DYNAMIC_STATE_STENCIL_REFERENCE + 1,
+   TU_DYNAMIC_STATE_COUNT,
+};
+
+enum tu_draw_state_group_id
+{
+   TU_DRAW_STATE_PROGRAM,
+   TU_DRAW_STATE_PROGRAM_BINNING,
+   TU_DRAW_STATE_VB,
+   TU_DRAW_STATE_VI,
+   TU_DRAW_STATE_VI_BINNING,
+   TU_DRAW_STATE_RAST,
+   TU_DRAW_STATE_DS,
+   TU_DRAW_STATE_BLEND,
+   TU_DRAW_STATE_VS_CONST,
+   TU_DRAW_STATE_GS_CONST,
+   TU_DRAW_STATE_FS_CONST,
+   TU_DRAW_STATE_DESC_SETS,
+   TU_DRAW_STATE_DESC_SETS_LOAD,
+   TU_DRAW_STATE_VS_PARAMS,
+   TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
+   TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
+
+   /* dynamic state related draw states */
+   TU_DRAW_STATE_DYNAMIC,
+   TU_DRAW_STATE_COUNT = TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_COUNT,
+};
+
 enum tu_cs_mode
 {
 
@@ -578,73 +616,12 @@ tu_buffer_iova(struct tu_buffer *buffer)
    return buffer->bo->iova + buffer->bo_offset;
 }
 
-enum tu_dynamic_state_bits
-{
-   TU_DYNAMIC_VIEWPORT = 1 << 0,
-   TU_DYNAMIC_SCISSOR = 1 << 1,
-   TU_DYNAMIC_LINE_WIDTH = 1 << 2,
-   TU_DYNAMIC_DEPTH_BIAS = 1 << 3,
-   TU_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
-   TU_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
-   TU_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
-   TU_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
-   TU_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
-   TU_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
-   TU_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
-   TU_DYNAMIC_ALL = (1 << 11) - 1,
-};
-
 struct tu_vertex_binding
 {
    struct tu_buffer *buffer;
    VkDeviceSize offset;
 };
 
-struct tu_viewport_state
-{
-   uint32_t count;
-   VkViewport viewports[MAX_VIEWPORTS];
-};
-
-struct tu_scissor_state
-{
-   uint32_t count;
-   VkRect2D scissors[MAX_SCISSORS];
-};
-
-struct tu_dynamic_state
-{
-   /**
-    * Bitmask of (1 << VK_DYNAMIC_STATE_*).
-    * Defines the set of saved dynamic state.
-    */
-   uint32_t mask;
-
-   struct tu_viewport_state viewport;
-
-   struct tu_scissor_state scissor;
-
-   float line_width;
-
-   struct
-   {
-      uint32_t front;
-      uint32_t back;
-   } stencil_compare_mask;
-
-   struct
-   {
-      uint32_t front;
-      uint32_t back;
-   } stencil_write_mask;
-
-   struct
-   {
-      uint32_t front;
-      uint32_t back;
-   } stencil_reference;
-};
-
 const char *
 tu_get_debug_option_name(int id);
 
@@ -654,11 +631,7 @@ tu_get_perftest_option_name(int id);
 struct tu_descriptor_state
 {
    struct tu_descriptor_set *sets[MAX_SETS];
-   uint32_t valid;
-   struct tu_push_descriptor_set push_set;
-   bool push_dirty;
    uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
-   uint32_t input_attachments[MAX_RTS * A6XX_TEX_CONST_DWORDS];
 };
 
 struct tu_tile
@@ -693,21 +666,14 @@ struct tu_tiling_config
 
 enum tu_cmd_dirty_bits
 {
-   TU_CMD_DIRTY_PIPELINE = 1 << 0,
    TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
    TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
-
    TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
    TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
    TU_CMD_DIRTY_SHADER_CONSTS = 1 << 5,
    TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
-
-   TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
-   TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
-   TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
-   TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
-   TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
-   TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
+   /* all draw states were disabled and need to be re-enabled: */
+   TU_CMD_DIRTY_DRAW_STATE = 1 << 7,
 };
 
 struct tu_streamout_state {
@@ -842,7 +808,18 @@ struct tu_cmd_state
       VkDeviceSize offsets[MAX_VBS];
    } vb;
 
-   struct tu_dynamic_state dynamic;
+   /* for dynamic states that can't be emitted directly */
+   uint32_t dynamic_stencil_mask;
+   uint32_t dynamic_stencil_wrmask;
+   uint32_t dynamic_stencil_ref;
+   uint32_t dynamic_gras_su_cntl;
+
+   /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */
+   struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
+   struct tu_cs_entry vertex_buffers_ib;
+   struct tu_cs_entry shader_const_ib[MESA_SHADER_STAGES];
+   struct tu_cs_entry desc_sets_ib, desc_sets_load_ib;
+   struct tu_cs_entry ia_gmem_ib, ia_sysmem_ib;
 
    /* Stream output buffers */
    struct
@@ -1032,31 +1009,6 @@ struct tu_event
    struct tu_bo bo;
 };
 
-static inline gl_shader_stage
-vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
-{
-   assert(__builtin_popcount(vk_stage) == 1);
-   return ffs(vk_stage) - 1;
-}
-
-static inline VkShaderStageFlagBits
-mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
-{
-   return (1 << mesa_stage);
-}
-
-#define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
-
-#define tu_foreach_stage(stage, stage_bits)                                  \
-   for (gl_shader_stage stage,                                               \
-        __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK);              \
-        stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
-
-uint32_t
-tu6_stage2opcode(gl_shader_stage type);
-enum a6xx_state_block
-tu6_stage2shadersb(gl_shader_stage type);
-
 struct tu_shader_module
 {
    unsigned char sha1[20];
@@ -1076,7 +1028,6 @@ struct tu_shader
    struct ir3_shader *ir3_shader;
 
    struct tu_push_constant_range push_consts;
-   unsigned attachment_idx[MAX_RTS];
    uint8_t active_desc_sets;
 };
 
@@ -1094,7 +1045,6 @@ tu_shader_destroy(struct tu_device *dev,
 
 struct tu_program_descriptor_linkage
 {
-   struct ir3_ubo_analysis_state ubo_state;
    struct ir3_const_state const_state;
 
    uint32_t constlen;
@@ -1106,8 +1056,6 @@ struct tu_pipeline
 {
    struct tu_cs cs;
 
-   struct tu_dynamic_state dynamic_state;
-
    struct tu_pipeline_layout *layout;
 
    bool need_indirect_descriptor_sets;
@@ -1116,6 +1064,15 @@ struct tu_pipeline
 
    struct tu_streamout_state streamout;
 
+   /* mask of enabled dynamic states
+    * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
+    */
+   uint32_t dynamic_state_mask;
+   struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
+
+   /* gras_su_cntl without line width, used for dynamic line width state */
+   uint32_t gras_su_cntl;
+
    struct
    {
       struct tu_bo binary_bo;
@@ -1123,7 +1080,6 @@ struct tu_pipeline
       struct tu_cs_entry binning_state_ib;
 
       struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
-      unsigned input_attachment_idx[MAX_RTS];
    } program;
 
    struct
@@ -1147,12 +1103,6 @@ struct tu_pipeline
    struct
    {
       struct tu_cs_entry state_ib;
-   } vp;
-
-   struct
-   {
-      uint32_t gras_su_cntl;
-      struct tu_cs_entry state_ib;
    } rast;
 
    struct
@@ -1180,31 +1130,12 @@ tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
 void
 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc);
 
-void
-tu6_emit_gras_su_cntl(struct tu_cs *cs,
-                      uint32_t gras_su_cntl,
-                      float line_width);
-
 void
 tu6_emit_depth_bias(struct tu_cs *cs,
                     float constant_factor,
                     float clamp,
                     float slope_factor);
 
-void
-tu6_emit_stencil_compare_mask(struct tu_cs *cs,
-                              uint32_t front,
-                              uint32_t back);
-
-void
-tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
-
-void
-tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
-
-void
-tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
-
 void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
 
 void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
@@ -1291,8 +1222,6 @@ tu6_base_format(VkFormat format)
    return tu6_format_color(format, TILE6_LINEAR).fmt;
 }
 
-enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
-
 struct tu_image
 {
    VkImageType type;
@@ -1341,11 +1270,6 @@ tu_get_levelCount(const struct tu_image *image,
              : range->levelCount;
 }
 
-enum a3xx_msaa_samples
-tu_msaa_samples(uint32_t samples);
-enum a6xx_tex_fetchsize
-tu6_fetchsize(VkFormat format);
-
 struct tu_image_view
 {
    struct tu_image *image; /**< VkImageViewCreateInfo::image */
@@ -1406,9 +1330,6 @@ tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t
 void
 tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
 
-enum a6xx_tex_filter
-tu6_tex_filter(VkFilter filter, unsigned aniso);
-
 VkResult
 tu_image_create(VkDevice _device,
                 const VkImageCreateInfo *pCreateInfo,