#include <valgrind.h>
#define VG(x) x
#else
-#define VG(x)
+#define VG(x) ((void)0)
#endif
#include "c11/threads.h"
#include "adreno_common.xml.h"
#include "adreno_pm4.xml.h"
#include "a6xx.xml.h"
+#include "fdl/freedreno_layout.h"
#include "tu_descriptor_set.h"
#include "tu_extensions.h"
#include "tu_entrypoints.h"
+#include "vk_format.h"
+
#define MAX_VBS 32
#define MAX_VERTEX_ATTRIBS 32
#define MAX_RTS 8
#define NUM_META_FS_KEYS 13
#define TU_MAX_DRM_DEVICES 8
#define MAX_VIEWS 8
+/* The Qualcomm driver exposes 0x20000058 */
+#define MAX_STORAGE_BUFFER_RANGE 0x20000000
+/* We use ldc for uniform buffer loads, just like the Qualcomm driver, so
+ * expose the same maximum range.
+ * TODO: The SIZE bitfield is 15 bits, and in 4-dword units, so the actual
+ * range might be higher.
+ */
+#define MAX_UNIFORM_BUFFER_RANGE 0x10000
#define NUM_DEPTH_CLEAR_PIPELINES 3
unsigned gpu_id;
uint32_t gmem_size;
- uint32_t tile_align_w;
- uint32_t tile_align_h;
+ uint64_t gmem_base;
+ uint32_t ccu_offset_gmem;
+ uint32_t ccu_offset_bypass;
+#define GMEM_ALIGN_W 16
+#define GMEM_ALIGN_H 4
+
+ struct {
+ uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
+ uint32_t PC_UNKNOWN_9805;
+ uint32_t SP_UNKNOWN_A0F8;
+ } magic;
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
TU_DEBUG_STARTUP = 1 << 0,
TU_DEBUG_NIR = 1 << 1,
TU_DEBUG_IR3 = 1 << 2,
+ TU_DEBUG_NOBIN = 1 << 3,
+ TU_DEBUG_SYSMEM = 1 << 4,
+ TU_DEBUG_FORCEBIN = 1 << 5,
};
struct tu_instance
struct tu_fence
{
+ struct wsi_fence *fence_wsi;
bool signaled;
int fd;
};
struct tu_fence submit_fence;
};
+struct tu_bo
+{
+ uint32_t gem_handle;
+ uint64_t size;
+ uint64_t iova;
+ void *map;
+};
+
struct tu_device
{
VK_LOADER_DATA _loader_data;
/* Backup in-memory cache to be used if the app doesn't provide one */
struct tu_pipeline_cache *mem_cache;
+ struct tu_bo vsc_data;
+ struct tu_bo vsc_data2;
+ uint32_t vsc_data_pitch;
+ uint32_t vsc_data2_pitch;
+
+ struct tu_bo border_color;
+
struct list_head shader_slabs;
mtx_t shader_slab_mutex;
struct tu_device_extension_table enabled_extensions;
};
-struct tu_bo
-{
- uint32_t gem_handle;
- uint64_t size;
- uint64_t iova;
- void *map;
-};
-
VkResult
tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
VkResult
uint32_t offset;
};
+struct ts_cs_memory {
+ uint32_t *map;
+ uint64_t iova;
+};
+
enum tu_cs_mode
{
uint32_t *reserved_end;
uint32_t *end;
+ struct tu_device *device;
enum tu_cs_mode mode;
uint32_t next_bo_size;
struct tu_bo **bos;
uint32_t bo_count;
uint32_t bo_capacity;
+
+ /* state for cond_exec_start/cond_exec_end */
+ uint32_t cond_flags;
+ uint32_t *cond_dwords;
};
struct tu_device_memory
struct tu_descriptor_set
{
const struct tu_descriptor_set_layout *layout;
+ struct tu_descriptor_pool *pool;
uint32_t size;
uint64_t va;
uint32_t *mapped_ptr;
- struct tu_descriptor_range *dynamic_descriptors;
- struct tu_bo *descriptors[0];
+ uint32_t *dynamic_descriptors;
+
+ struct tu_bo *buffers[0];
};
struct tu_push_descriptor_set
struct tu_descriptor_update_template
{
uint32_t entry_count;
- VkPipelineBindPoint bind_point;
struct tu_descriptor_update_template_entry entry[0];
};
VkDeviceSize bo_offset;
};
+static inline uint64_t
+tu_buffer_iova(struct tu_buffer *buffer)
+{
+ return buffer->bo->iova + buffer->bo_offset;
+}
+
enum tu_dynamic_state_bits
{
TU_DYNAMIC_VIEWPORT = 1 << 0,
const char *
tu_get_perftest_option_name(int id);
-/**
- * Attachment state when recording a renderpass instance.
- *
- * The clear value is valid only if there exists a pending clear.
- */
-struct tu_attachment_state
-{
- VkImageAspectFlags pending_clear_aspects;
- uint32_t cleared_views;
- VkClearValue clear_value;
- VkImageLayout current_layout;
-};
-
struct tu_descriptor_state
{
struct tu_descriptor_set *sets[MAX_SETS];
- uint32_t dirty;
uint32_t valid;
struct tu_push_descriptor_set push_set;
bool push_dirty;
- uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
+ uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS];
+ uint32_t input_attachments[MAX_RTS * A6XX_TEX_CONST_DWORDS];
};
struct tu_tile
struct tu_tiling_config
{
VkRect2D render_area;
- uint32_t buffer_cpp[MAX_RTS + 2];
- uint32_t buffer_count;
/* position and size of the first tile */
VkRect2D tile0;
/* number of tiles */
VkExtent2D tile_count;
- uint32_t gmem_offsets[MAX_RTS + 2];
-
/* size of the first VSC pipe */
VkExtent2D pipe0;
/* number of VSC pipes */
/* pipe register values */
uint32_t pipe_config[MAX_VSC_PIPES];
uint32_t pipe_sizes[MAX_VSC_PIPES];
+
+ /* Whether sysmem rendering must be used */
+ bool force_sysmem;
};
enum tu_cmd_dirty_bits
{
TU_CMD_DIRTY_PIPELINE = 1 << 0,
- TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 1,
- TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 2,
+ TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
+ TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
+ TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
+ TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
+ TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 5,
+ TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
+ TU_CMD_DIRTY_INPUT_ATTACHMENTS = 1 << 7,
TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 18,
TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
+ TU_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 20,
+ TU_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 21,
+};
+
+struct tu_streamout_state {
+ uint16_t stride[IR3_MAX_SO_BUFFERS];
+ uint32_t ncomp[IR3_MAX_SO_BUFFERS];
+ uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
+ uint32_t prog_count;
+ uint32_t vpc_so_buf_cntl;
};
struct tu_cmd_state
uint32_t dirty;
struct tu_pipeline *pipeline;
+ struct tu_pipeline *compute_pipeline;
/* Vertex buffers */
struct
struct tu_dynamic_state dynamic;
+ /* Stream output buffers */
+ struct
+ {
+ struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
+ VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
+ VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
+ } streamout_buf;
+
+ uint8_t streamout_reset;
+ uint8_t streamout_enabled;
+
/* Index buffer */
struct tu_buffer *index_buffer;
uint64_t index_offset;
const struct tu_render_pass *pass;
const struct tu_subpass *subpass;
const struct tu_framebuffer *framebuffer;
- struct tu_attachment_state *attachments;
struct tu_tiling_config tiling_config;
- struct tu_cs_entry tile_load_ib;
struct tu_cs_entry tile_store_ib;
};
VkResult
tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
+/* This struct defines the layout of the scratch_bo */
+struct tu6_control
+{
+ uint32_t seqno; /* seqno for async CP_EVENT_WRITE, etc */
+ uint32_t _pad0;
+ volatile uint32_t vsc_overflow;
+ uint32_t _pad1;
+ /* flag set from cmdstream when VSC overflow detected: */
+ uint32_t vsc_scratch;
+ uint32_t _pad2;
+ uint32_t _pad3;
+ uint32_t _pad4;
+
+ /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
+ struct {
+ uint32_t offset;
+ uint32_t pad[7];
+ } flush_base[4];
+};
+
+#define ctrl_offset(member) offsetof(struct tu6_control, member)
+
struct tu_cmd_buffer
{
VK_LOADER_DATA _loader_data;
struct tu_bo_list bo_list;
struct tu_cs cs;
struct tu_cs draw_cs;
- struct tu_cs draw_state;
- struct tu_cs tile_cs;
-
- uint16_t marker_reg;
- uint32_t marker_seqno;
+ struct tu_cs draw_epilogue_cs;
+ struct tu_cs sub_cs;
struct tu_bo scratch_bo;
uint32_t scratch_seqno;
+ struct tu_bo vsc_data;
+ struct tu_bo vsc_data2;
+ uint32_t vsc_data_pitch;
+ uint32_t vsc_data2_pitch;
+ bool use_vsc_data;
+
bool wait_for_idle;
};
-void
+/* Temporary struct for tracking a register state to be written, used by
+ * a6xx-pack.h and tu_cs_emit_regs()
+ */
+struct tu_reg_value {
+ uint32_t reg;
+ uint64_t value;
+ bool is_address;
+ struct tu_bo *bo;
+ bool bo_write;
+ uint32_t bo_offset;
+ uint32_t bo_shift;
+};
+
+unsigned
tu6_emit_event_write(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
enum vgt_event_type event,
tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer,
VkPipelineBindPoint bind_point)
{
- assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
return &cmd_buffer->descriptors[bind_point];
}
bool include_binning_pass;
};
-struct tu_descriptor_map
+struct tu_push_constant_range
{
- unsigned num;
- int set[32];
- int binding[32];
+ uint32_t lo;
+ uint32_t count;
};
struct tu_shader
{
struct ir3_shader ir3_shader;
- struct tu_descriptor_map texture_map;
- struct tu_descriptor_map sampler_map;
- struct tu_descriptor_map ubo_map;
+ struct tu_push_constant_range push_consts;
+ unsigned attachment_idx[MAX_RTS];
/* This may be true for vertex shaders. When true, variants[1] is the
* binning variant and binning_binary is non-NULL.
tu_shader_create(struct tu_device *dev,
gl_shader_stage stage,
const VkPipelineShaderStageCreateInfo *stage_info,
+ struct tu_pipeline_layout *layout,
const VkAllocationCallbacks *alloc);
void
struct tu_program_descriptor_linkage
{
struct ir3_ubo_analysis_state ubo_state;
+ struct ir3_const_state const_state;
uint32_t constlen;
- uint32_t offset_ubo; /* ubo pointers const offset */
- uint32_t num_ubo; /* number of ubo pointers */
-
- struct tu_descriptor_map texture_map;
- struct tu_descriptor_map sampler_map;
- struct tu_descriptor_map ubo_map;
+ struct tu_push_constant_range push_consts;
};
struct tu_pipeline
bool need_indirect_descriptor_sets;
VkShaderStageFlags active_stages;
+ struct tu_streamout_state streamout;
+
struct
{
struct tu_bo binary_bo;
struct tu_cs_entry binning_state_ib;
struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
+ unsigned input_attachment_idx[MAX_RTS];
} program;
+ struct
+ {
+ struct tu_cs_entry state_ib;
+ } load_state;
+
struct
{
uint8_t bindings[MAX_VERTEX_ATTRIBS];
- uint16_t strides[MAX_VERTEX_ATTRIBS];
- uint16_t offsets[MAX_VERTEX_ATTRIBS];
uint32_t count;
uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
- uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
- uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
uint32_t binning_count;
struct tu_cs_entry state_ib;
{
struct tu_cs_entry state_ib;
} blend;
+
+ struct
+ {
+ uint32_t local_size[3];
+ } compute;
};
void
void
tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
+void tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits samples);
+
+void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2);
+
+void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
+
+struct tu_image_view;
+
+void
+tu_resolve_sysmem(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ struct tu_image_view *src,
+ struct tu_image_view *dst,
+ uint32_t layers,
+ const VkRect2D *rect);
+
+void
+tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t a,
+ const VkRenderPassBeginInfo *info);
+
+void
+tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t a,
+ const VkRenderPassBeginInfo *info);
+
+void
+tu_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
+
+/* expose this function to be able to emit load without checking LOAD_OP */
+void
+tu_emit_load_gmem_attachment(struct tu_cmd_buffer *cmd, struct tu_cs *cs, uint32_t a);
+
+/* note: gmem store can also resolve */
+void
+tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t a,
+ uint32_t gmem_a);
+
struct tu_userdata_info *
tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
gl_shader_stage stage,
uint32_t custom_blend_mode;
};
+enum tu_supported_formats {
+ FMT_VERTEX = 1,
+ FMT_TEXTURE = 2,
+ FMT_COLOR = 4,
+};
+
struct tu_native_format
{
- int vtx; /* VFMTn_xxx or -1 */
- int tex; /* TFMTn_xxx or -1 */
- int rb; /* RBn_xxx or -1 */
- int swap; /* enum a3xx_color_swap */
- bool present; /* internal only; always true to external users */
+ enum a6xx_format fmt : 8;
+ enum a3xx_color_swap swap : 8;
+ enum a6xx_tile_mode tile_mode : 8;
+ enum tu_supported_formats supported : 8;
};
-const struct tu_native_format *
-tu6_get_native_format(VkFormat format);
+struct tu_native_format tu6_format_vtx(VkFormat format);
+struct tu_native_format tu6_format_color(VkFormat format, enum a6xx_tile_mode tile_mode);
+struct tu_native_format tu6_format_texture(VkFormat format, enum a6xx_tile_mode tile_mode);
-void
-tu_pack_clear_value(const VkClearValue *val,
- VkFormat format,
- uint32_t buf[4]);
-enum a6xx_2d_ifmt tu6_rb_fmt_to_ifmt(enum a6xx_color_fmt fmt);
-enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
-
-struct tu_image_level
+static inline enum a6xx_format
+tu6_base_format(VkFormat format)
{
- VkDeviceSize offset;
- VkDeviceSize size;
- uint32_t pitch;
-};
+ /* note: tu6_format_color doesn't care about tiling for .fmt field */
+ return tu6_format_color(format, TILE6_LINEAR).fmt;
+}
+
+enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
struct tu_image
{
uint32_t layer_count;
VkSampleCountFlagBits samples;
-
- VkDeviceSize size;
- uint32_t alignment;
-
- /* memory layout */
- VkDeviceSize layer_size;
- struct tu_image_level levels[15];
- unsigned tile_mode;
- unsigned cpp;
+ struct fdl_layout layout;
unsigned queue_family_mask;
bool exclusive;
: range->levelCount;
}
+static inline VkDeviceSize
+tu_layer_size(struct tu_image *image, int level)
+{
+ return fdl_layer_stride(&image->layout, level);
+}
+
+static inline uint32_t
+tu_image_stride(struct tu_image *image, int level)
+{
+ return image->layout.slices[level].pitch * image->layout.cpp;
+}
+
+/* to get the right pitch for compressed formats */
+static inline uint32_t
+tu_image_pitch(struct tu_image *image, int level)
+{
+ uint32_t stride = tu_image_stride(image, level);
+ return stride / vk_format_get_blockwidth(image->vk_format);
+}
+
+static inline uint64_t
+tu_image_base(struct tu_image *image, int level, int layer)
+{
+ return image->bo->iova + image->bo_offset +
+ fdl_surface_offset(&image->layout, level, layer);
+}
+
+#define tu_image_base_ref(image, level, layer) \
+ .bo = image->bo, \
+ .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
+ level, layer))
+
+#define tu_image_view_base_ref(iview) \
+ tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
+
+static inline VkDeviceSize
+tu_image_ubwc_size(struct tu_image *image, int level)
+{
+ return image->layout.ubwc_layer_size;
+}
+
+static inline uint32_t
+tu_image_ubwc_pitch(struct tu_image *image, int level)
+{
+ return image->layout.ubwc_slices[level].pitch;
+}
+
+static inline uint64_t
+tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
+{
+ return image->layout.ubwc_slices[level].offset +
+ layer * tu_image_ubwc_size(image, level);
+}
+
+static inline uint64_t
+tu_image_ubwc_base(struct tu_image *image, int level, int layer)
+{
+ return image->bo->iova + image->bo_offset +
+ tu_image_ubwc_surface_offset(image, level, layer);
+}
+
+#define tu_image_ubwc_base_ref(image, level, layer) \
+ .bo = image->bo, \
+ .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
+ level, layer))
+
+#define tu_image_view_ubwc_base_ref(iview) \
+ tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
+
+#define tu_image_view_ubwc_pitches(iview) \
+ .pitch = tu_image_ubwc_pitch(iview->image, iview->base_mip), \
+ .array_pitch = tu_image_ubwc_size(iview->image, iview->base_mip) >> 2
+
enum a6xx_tile_mode
tu6_get_image_tile_mode(struct tu_image *image, int level);
enum a3xx_msaa_samples
tu_msaa_samples(uint32_t samples);
+enum a6xx_tex_fetchsize
+tu6_fetchsize(VkFormat format);
+
+static inline struct tu_native_format
+tu6_format_image(struct tu_image *image, VkFormat format, uint32_t level)
+{
+ struct tu_native_format fmt =
+ tu6_format_color(format, image->layout.tile_mode);
+ fmt.tile_mode = tu6_get_image_tile_mode(image, level);
+ return fmt;
+}
+
+static inline struct tu_native_format
+tu6_format_image_src(struct tu_image *image, VkFormat format, uint32_t level)
+{
+ struct tu_native_format fmt =
+ tu6_format_texture(format, image->layout.tile_mode);
+ fmt.tile_mode = tu6_get_image_tile_mode(image, level);
+ return fmt;
+}
struct tu_image_view
{
uint32_t storage_descriptor[A6XX_TEX_CONST_DWORDS];
};
-struct tu_sampler
-{
- uint32_t state[A6XX_TEX_SAMP_DWORDS];
-
- bool needs_border;
-};
-
-struct tu_image_create_info
-{
- const VkImageCreateInfo *vk_info;
- bool scanout;
- bool no_metadata_planes;
+struct tu_sampler {
+ uint32_t descriptor[A6XX_TEX_SAMP_DWORDS];
};
VkResult
tu_image_create(VkDevice _device,
- const struct tu_image_create_info *info,
+ const VkImageCreateInfo *pCreateInfo,
const VkAllocationCallbacks *alloc,
- VkImage *pImage);
+ VkImage *pImage,
+ uint64_t modifier);
VkResult
tu_image_from_gralloc(VkDevice device_h,
struct tu_buffer_view
{
- VkFormat vk_format;
- uint64_t range; /**< VkBufferViewCreateInfo::range */
- uint32_t state[4];
+ uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
+
+ struct tu_buffer *buffer;
};
void
tu_buffer_view_init(struct tu_buffer_view *view,
struct tu_attachment_info attachments[0];
};
-struct tu_subpass_barrier
-{
- VkPipelineStageFlags src_stage_mask;
- VkAccessFlags src_access_mask;
- VkAccessFlags dst_access_mask;
-};
-
-void
-tu_subpass_barrier(struct tu_cmd_buffer *cmd_buffer,
- const struct tu_subpass_barrier *barrier);
-
struct tu_subpass_attachment
{
uint32_t attachment;
- VkImageLayout layout;
};
struct tu_subpass
struct tu_subpass_attachment *resolve_attachments;
struct tu_subpass_attachment depth_stencil_attachment;
- /** Subpass has at least one resolve attachment */
- bool has_resolve;
-
- struct tu_subpass_barrier start_barrier;
-
- uint32_t view_mask;
- VkSampleCountFlagBits max_sample_count;
+ VkSampleCountFlagBits samples;
};
struct tu_render_pass_attachment
{
VkFormat format;
uint32_t samples;
+ uint32_t cpp;
VkAttachmentLoadOp load_op;
VkAttachmentLoadOp stencil_load_op;
- VkImageLayout initial_layout;
- VkImageLayout final_layout;
- uint32_t view_mask;
+ VkAttachmentStoreOp store_op;
+ VkAttachmentStoreOp stencil_store_op;
+ int32_t gmem_offset;
};
struct tu_render_pass
{
uint32_t attachment_count;
uint32_t subpass_count;
+ uint32_t gmem_pixels;
struct tu_subpass_attachment *subpass_attachments;
struct tu_render_pass_attachment *attachments;
- struct tu_subpass_barrier end_barrier;
struct tu_subpass subpasses[0];
};
struct tu_query_pool
{
+ VkQueryType type;
uint32_t stride;
- uint32_t availability_offset;
uint64_t size;
- char *ptr;
- VkQueryType type;
- uint32_t pipeline_stats_mask;
+ uint32_t pipeline_statistics;
+ struct tu_bo bo;
};
struct tu_semaphore
int
tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
+int
+tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
+
int
tu_drm_submitqueue_new(const struct tu_device *dev,
int priority,
projects / mesa.git / blobdiff