unsigned gpu_id;
uint32_t gmem_size;
+ uint64_t gmem_base;
uint32_t tile_align_w;
uint32_t tile_align_h;
+ struct {
+ uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */
+ uint32_t RB_CCU_CNTL_gmem; /* for GMEM */
+ uint32_t PC_UNKNOWN_9805;
+ uint32_t SP_UNKNOWN_A0F8;
+ } magic;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
TU_DEBUG_NIR = 1 << 1,
TU_DEBUG_IR3 = 1 << 2,
TU_DEBUG_NOBIN = 1 << 3,
+ TU_DEBUG_SYSMEM = 1 << 4,
+ TU_DEBUG_FORCEBIN = 1 << 5,
};
struct tu_instance
struct tu_fence submit_fence;
};
+struct tu_bo
+{
+ uint32_t gem_handle;
+ uint64_t size;
+ uint64_t iova;
+ void *map;
+};
+
struct tu_device
{
VK_LOADER_DATA _loader_data;
/* Backup in-memory cache to be used if the app doesn't provide one */
struct tu_pipeline_cache *mem_cache;
+ struct tu_bo vsc_data;
+ struct tu_bo vsc_data2;
+ uint32_t vsc_data_pitch;
+ uint32_t vsc_data2_pitch;
+
struct list_head shader_slabs;
mtx_t shader_slab_mutex;
struct tu_device_extension_table enabled_extensions;
};
-struct tu_bo
-{
- uint32_t gem_handle;
- uint64_t size;
- uint64_t iova;
- void *map;
-};
-
VkResult
tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
VkResult
uint32_t *reserved_end;
uint32_t *end;
+ struct tu_device *device;
enum tu_cs_mode mode;
uint32_t next_bo_size;
struct tu_bo **bos;
uint32_t bo_count;
uint32_t bo_capacity;
+
+ /* state for cond_exec_start/cond_exec_end */
+ uint32_t cond_flags;
+ uint32_t *cond_dwords;
};
struct tu_device_memory
struct tu_descriptor_state
{
struct tu_descriptor_set *sets[MAX_SETS];
- uint32_t dirty;
uint32_t valid;
struct tu_push_descriptor_set push_set;
bool push_dirty;
/* pipe register values */
uint32_t pipe_config[MAX_VSC_PIPES];
uint32_t pipe_sizes[MAX_VSC_PIPES];
+
+ /* Whether sysmem rendering must be used */
+ bool force_sysmem;
};
enum tu_cmd_dirty_bits
TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
+ TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 5,
TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
};
+struct tu_streamout_state {
+ uint16_t stride[IR3_MAX_SO_BUFFERS];
+ uint32_t ncomp[IR3_MAX_SO_BUFFERS];
+ uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
+ uint32_t prog_count;
+ uint32_t vpc_so_buf_cntl;
+};
+
struct tu_cmd_state
{
uint32_t dirty;
struct tu_dynamic_state dynamic;
+ /* Stream output buffers */
+ struct
+ {
+ struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
+ VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
+ VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
+ } streamout_buf;
+
+ uint8_t streamout_reset;
+ uint8_t streamout_enabled;
+
/* Index buffer */
struct tu_buffer *index_buffer;
uint64_t index_offset;
struct tu_tiling_config tiling_config;
- struct tu_cs_entry tile_load_ib;
struct tu_cs_entry tile_store_ib;
};
struct tu_bo_list bo_list;
struct tu_cs cs;
struct tu_cs draw_cs;
+ struct tu_cs draw_epilogue_cs;
struct tu_cs sub_cs;
- uint16_t marker_reg;
- uint32_t marker_seqno;
-
struct tu_bo scratch_bo;
uint32_t scratch_seqno;
#define VSC_OVERFLOW 0x8
#define VSC_SCRATCH 0x10
+#define VSC_FLUSH 0x20
struct tu_bo vsc_data;
struct tu_bo vsc_data2;
bool wait_for_idle;
};
+/* Temporary struct for tracking a register state to be written, used by
+ * a6xx-pack.h and tu_cs_emit_regs()
+ */
+struct tu_reg_value {
+ uint32_t reg;
+ uint64_t value;
+ bool is_address;
+ struct tu_bo *bo;
+ bool bo_write;
+ uint32_t bo_offset;
+ uint32_t bo_shift;
+};
+
unsigned
tu6_emit_event_write(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
/* TODO: avoid fixed size array/justify the size */
unsigned num; /* number of array entries */
unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
- int set[64];
- int binding[64];
- int value[64];
- int array_size[64];
+ int set[128];
+ int binding[128];
+ int value[128];
+ int array_size[128];
};
struct tu_shader
bool need_indirect_descriptor_sets;
VkShaderStageFlags active_stages;
+ struct tu_streamout_state streamout;
+
struct
{
struct tu_bo binary_bo;
uint32_t custom_blend_mode;
};
+enum tu_supported_formats {
+ FMT_VERTEX = 1,
+ FMT_TEXTURE = 2,
+ FMT_COLOR = 4,
+};
+
struct tu_native_format
{
- int vtx; /* VFMTn_xxx or -1 */
- int tex; /* TFMTn_xxx or -1 */
- int rb; /* RBn_xxx or -1 */
- int swap; /* enum a3xx_color_swap */
- bool present; /* internal only; always true to external users */
+ enum a6xx_format fmt : 8;
+ enum a3xx_color_swap swap : 8;
+ enum tu_supported_formats supported : 8;
};
-const struct tu_native_format *
-tu6_get_native_format(VkFormat format);
+struct tu_native_format tu6_get_native_format(VkFormat format);
+struct tu_native_format tu6_format_vtx(VkFormat format);
+enum a6xx_format tu6_format_gmem(VkFormat format);
+struct tu_native_format tu6_format_color(VkFormat format, bool tiled);
+struct tu_native_format tu6_format_texture(VkFormat format, bool tiled);
void
tu_pack_clear_value(const VkClearValue *val,
void
tu_2d_clear_zs(const VkClearDepthStencilValue *val, VkFormat format, uint32_t buf[4]);
-enum a6xx_2d_ifmt tu6_rb_fmt_to_ifmt(enum a6xx_color_fmt fmt);
+enum a6xx_2d_ifmt tu6_fmt_to_ifmt(enum a6xx_format fmt);
enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
struct tu_image_level
fdl_surface_offset(&image->layout, level, layer);
}
+#define tu_image_base_ref(image, level, layer) \
+ .bo = image->bo, \
+ .bo_offset = (image->bo_offset + fdl_surface_offset(&image->layout, \
+ level, layer))
+
+#define tu_image_view_base_ref(iview) \
+ tu_image_base_ref(iview->image, iview->base_mip, iview->base_layer)
+
static inline VkDeviceSize
tu_image_ubwc_size(struct tu_image *image, int level)
{
- return image->layout.ubwc_size;
+ return image->layout.ubwc_layer_size;
}
static inline uint32_t
return image->layout.ubwc_slices[level].pitch;
}
+static inline uint64_t
+tu_image_ubwc_surface_offset(struct tu_image *image, int level, int layer)
+{
+ return image->layout.ubwc_slices[level].offset +
+ layer * tu_image_ubwc_size(image, level);
+}
+
static inline uint64_t
tu_image_ubwc_base(struct tu_image *image, int level, int layer)
{
return image->bo->iova + image->bo_offset +
- image->layout.ubwc_slices[level].offset +
- layer * tu_image_ubwc_size(image, level);
+ tu_image_ubwc_surface_offset(image, level, layer);
}
+#define tu_image_ubwc_base_ref(image, level, layer) \
+ .bo = image->bo, \
+ .bo_offset = (image->bo_offset + tu_image_ubwc_surface_offset(image, \
+ level, layer))
+
+#define tu_image_view_ubwc_base_ref(iview) \
+ tu_image_ubwc_base_ref(iview->image, iview->base_mip, iview->base_layer)
+
enum a6xx_tile_mode
tu6_get_image_tile_mode(struct tu_image *image, int level);
enum a3xx_msaa_samples
struct tu_buffer_view
{
- VkFormat vk_format;
- uint64_t range; /**< VkBufferViewCreateInfo::range */
- uint32_t state[4];
+ uint32_t descriptor[A6XX_TEX_CONST_DWORDS];
+
+ struct tu_buffer *buffer;
};
void
tu_buffer_view_init(struct tu_buffer_view *view,
struct tu_query_pool
{
+ VkQueryType type;
uint32_t stride;
- uint32_t availability_offset;
uint64_t size;
- char *ptr;
- VkQueryType type;
- uint32_t pipeline_stats_mask;
+ uint32_t pipeline_statistics;
+ struct tu_bo bo;
};
struct tu_semaphore
int
tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
+int
+tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
+
int
tu_drm_submitqueue_new(const struct tu_device *dev,
int priority,
uint64_t
tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
+
+void
+tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t attachment,
+ const VkClearValue *value,
+ const VkClearRect *rect);
+
+void
+tu_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t attachment,
+ uint8_t component_mask,
+ const VkClearValue *value);
+
#define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
\
static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
projects / mesa.git / blobdiff