unsigned gpu_id;
uint32_t gmem_size;
+ uint64_t gmem_base;
uint32_t tile_align_w;
uint32_t tile_align_h;
TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
+ TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 5,
TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 19,
};
+struct tu_streamout_state {
+ uint16_t stride[IR3_MAX_SO_BUFFERS];
+ uint32_t ncomp[IR3_MAX_SO_BUFFERS];
+ uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
+ uint32_t prog_count;
+ uint32_t vpc_so_buf_cntl;
+};
+
struct tu_cmd_state
{
uint32_t dirty;
struct tu_dynamic_state dynamic;
+ /* Stream output buffers */
+ struct
+ {
+ struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
+ VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
+ VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
+ } streamout_buf;
+
+ uint8_t streamout_reset;
+ uint8_t streamout_enabled;
+
/* Index buffer */
struct tu_buffer *index_buffer;
uint64_t index_offset;
uint32_t scratch_seqno;
#define VSC_OVERFLOW 0x8
#define VSC_SCRATCH 0x10
+#define VSC_FLUSH 0x20
struct tu_bo vsc_data;
struct tu_bo vsc_data2;
/* TODO: avoid fixed size array/justify the size */
unsigned num; /* number of array entries */
unsigned num_desc; /* Number of descriptors (sum of array_size[]) */
- int set[64];
- int binding[64];
- int value[64];
- int array_size[64];
+ int set[128];
+ int binding[128];
+ int value[128];
+ int array_size[128];
};
struct tu_shader
bool need_indirect_descriptor_sets;
VkShaderStageFlags active_stages;
+ struct tu_streamout_state streamout;
+
struct
{
struct tu_bo binary_bo;
int
tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
+int
+tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
+
int
tu_drm_submitqueue_new(const struct tu_device *dev,
int priority,