#include "vk_debug_report.h"
#include "wsi_common.h"
-#include "drm-uapi/msm_drm.h"
#include "ir3/ir3_compiler.h"
#include "ir3/ir3_shader.h"
#define tu_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
-static inline uint32_t
-tu_minify(uint32_t n, uint32_t levels)
-{
- if (unlikely(n == 0))
- return 0;
- else
- return MAX2(n >> levels, 1);
-}
-
#define for_each_bit(b, dword) \
for (uint32_t __dword = (dword); \
(b) = __builtin_ffs(__dword) - 1, __dword; __dword &= ~(1 << (b)))
-#define typed_memcpy(dest, src, count) \
- ({ \
- STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
- memcpy((dest), (src), (count) * sizeof(*(src))); \
- })
-
#define COND(bool, val) ((bool) ? (val) : 0)
#define BIT(bit) (1u << (bit))
int msm_major_version;
int msm_minor_version;
+ bool limited_z24s8;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
GLOBAL_SH_COUNT,
};
+#define TU_BORDER_COLOR_COUNT 4096
+#define TU_BORDER_COLOR_BUILTIN 6
+
/* This struct defines the layout of the global_bo */
struct tu6_global
{
- /* 6 bcolor_entry entries, one for each VK_BORDER_COLOR */
- uint8_t border_color[128 * 6];
-
/* clear/blit shaders, all <= 16 instrs (16 instr = 1 instrlen unit) */
instr_t shaders[GLOBAL_SH_COUNT][16];
volatile uint32_t vsc_draw_overflow;
uint32_t _pad1;
volatile uint32_t vsc_prim_overflow;
- uint32_t _pad2[3];
+ uint32_t _pad2;
+ uint64_t predicate;
/* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
struct {
uint32_t offset;
uint32_t pad[7];
} flush_base[4];
+
+ /* note: larger global bo will be used for customBorderColors */
+ struct bcolor_entry bcolor_builtin[TU_BORDER_COLOR_BUILTIN], bcolor[];
};
#define gb_offset(member) offsetof(struct tu6_global, member)
#define global_iova(cmd, member) ((cmd)->device->global_bo.iova + gb_offset(member))
uint32_t vsc_draw_strm_pitch;
uint32_t vsc_prim_strm_pitch;
- mtx_t vsc_pitch_mtx;
+ BITSET_DECLARE(custom_border_color, TU_BORDER_COLOR_COUNT);
+ mtx_t mutex;
};
VkResult _tu_device_set_lost(struct tu_device *device,
struct tu_cs_entry tile_store_ib;
bool xfb_used;
+ bool has_tess;
+ bool has_subpass_predication;
+ bool predication_active;
};
struct tu_cmd_pool
TU_CMD_BUFFER_STATUS_PENDING,
};
+#ifndef MSM_SUBMIT_BO_READ
+#define MSM_SUBMIT_BO_READ 0x0001
+#define MSM_SUBMIT_BO_WRITE 0x0002
+#define MSM_SUBMIT_BO_DUMP 0x0004
+
+struct drm_msm_gem_submit_bo {
+ uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */
+ uint32_t handle; /* in, GEM handle */
+ uint64_t presumed; /* in/out, presumed buffer address */
+};
+#endif
+
struct tu_bo_list
{
uint32_t count;
struct tu_cs draw_epilogue_cs;
struct tu_cs sub_cs;
- bool has_tess;
-
uint32_t vsc_draw_strm_pitch;
uint32_t vsc_prim_strm_pitch;
};
const struct ir3_shader_variant *hs,
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
- const struct ir3_shader_variant *fs);
+ const struct ir3_shader_variant *fs,
+ uint32_t patch_control_points,
+ bool vshs_workgroup);
void
tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
uint32_t RB_2D_DST_INFO;
uint32_t RB_BLIT_DST_INFO;
+
+ /* for d32s8 separate stencil */
+ uint64_t stencil_base_addr;
+ uint32_t stencil_layer_size;
+ uint32_t stencil_PITCH;
};
struct tu_sampler_ycbcr_conversion {
void
tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
+void
+tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
+
+#define tu_image_view_stencil(iview, x) \
+ ((iview->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT))
+
VkResult
tu_image_create(VkDevice _device,
const VkImageCreateInfo *pCreateInfo,
VkImage *out_image_h);
void
-tu_image_view_init(struct tu_image_view *view,
- const VkImageViewCreateInfo *pCreateInfo);
+tu_image_view_init(struct tu_image_view *iview,
+ const VkImageViewCreateInfo *pCreateInfo,
+ bool limited_z24s8);
struct tu_buffer_view
{
bool load;
bool store;
int32_t gmem_offset;
+ /* for D32S8 separate stencil: */
+ bool load_stencil;
+ bool store_stencil;
+ int32_t gmem_offset_stencil;
};
struct tu_render_pass
VkDescriptorUpdateTemplate descriptorUpdateTemplate,
const void *pData);
-int
-tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
-
-int
-tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
-
-int
-tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base);
+VkResult
+tu_physical_device_init(struct tu_physical_device *device,
+ struct tu_instance *instance);
+VkResult
+tu_enumerate_devices(struct tu_instance *instance);
int
tu_drm_submitqueue_new(const struct tu_device *dev,
void
tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
-uint32_t
-tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
-uint32_t
-tu_gem_import_dmabuf(const struct tu_device *dev,
- int prime_fd,
- uint64_t size);
-int
-tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
-void
-tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
-uint64_t
-tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
-uint64_t
-tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
-
#define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
\
static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \
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