#include "vk_alloc.h"
#include "vk_debug_report.h"
+#include "drm/msm_drm.h"
+#include "ir3/ir3_compiler.h"
+#include "ir3/ir3_shader.h"
+
+#include "adreno_common.xml.h"
+#include "adreno_pm4.xml.h"
+#include "a6xx.xml.h"
+
#include "tu_descriptor_set.h"
#include "tu_extensions.h"
#include <vulkan/vulkan.h>
#include <vulkan/vulkan_intel.h>
-#include "drm/freedreno_ringbuffer.h"
#include "tu_entrypoints.h"
#define MAX_VBS 32
#define MAX_VERTEX_ATTRIBS 32
#define MAX_RTS 8
-#define MAX_VIEWPORTS 16
+#define MAX_VSC_PIPES 32
+#define MAX_VIEWPORTS 1
#define MAX_SCISSORS 16
#define MAX_DISCARD_RECTANGLES 4
#define MAX_PUSH_CONSTANTS_SIZE 128
int local_fd;
int master_fd;
- struct fd_device *drm_device;
unsigned gpu_id;
uint32_t gmem_size;
+ uint32_t tile_align_w;
+ uint32_t tile_align_h;
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
enum tu_debug_flags
{
TU_DEBUG_STARTUP = 1 << 0,
+ TU_DEBUG_NIR = 1 << 1,
+ TU_DEBUG_IR3 = 1 << 2,
};
struct tu_instance
#define TU_MAX_QUEUE_FAMILIES 1
+struct tu_fence
+{
+ bool signaled;
+ int fd;
+};
+
+void
+tu_fence_init(struct tu_fence *fence, bool signaled);
+void
+tu_fence_finish(struct tu_fence *fence);
+void
+tu_fence_update_fd(struct tu_fence *fence, int fd);
+void
+tu_fence_copy(struct tu_fence *fence, const struct tu_fence *src);
+void
+tu_fence_signal(struct tu_fence *fence);
+void
+tu_fence_wait_idle(struct tu_fence *fence);
+
struct tu_queue
{
VK_LOADER_DATA _loader_data;
VkDeviceQueueCreateFlags flags;
uint32_t msm_queue_id;
+ struct tu_fence submit_fence;
};
struct tu_device
struct tu_physical_device *physical_device;
+ struct ir3_compiler *compiler;
+
/* Backup in-memory cache to be used if the app doesn't provide one */
struct tu_pipeline_cache *mem_cache;
{
uint32_t gem_handle;
uint64_t size;
- uint64_t offset;
uint64_t iova;
void *map;
};
VkResult
tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size);
+VkResult
+tu_bo_init_dmabuf(struct tu_device *dev,
+ struct tu_bo *bo,
+ uint64_t size,
+ int fd);
+int
+tu_bo_export_dmabuf(struct tu_device *dev, struct tu_bo *bo);
void
tu_bo_finish(struct tu_device *dev, struct tu_bo *bo);
VkResult
tu_bo_map(struct tu_device *dev, struct tu_bo *bo);
+struct tu_cs_entry
+{
+ /* No ownership */
+ const struct tu_bo *bo;
+
+ uint32_t size;
+ uint32_t offset;
+};
+
+enum tu_cs_mode
+{
+
+ /*
+ * A command stream in TU_CS_MODE_GROW mode grows automatically whenever it
+ * is full. tu_cs_begin must be called before command packet emission and
+ * tu_cs_end must be called after.
+ *
+ * This mode may create multiple entries internally. The entries must be
+ * submitted together.
+ */
+ TU_CS_MODE_GROW,
+
+ /*
+ * A command stream in TU_CS_MODE_EXTERNAL mode wraps an external,
+ * fixed-size buffer. tu_cs_begin and tu_cs_end are optional and have no
+ * effect on it.
+ *
+ * This mode does not create any entry or any BO.
+ */
+ TU_CS_MODE_EXTERNAL,
+
+ /*
+ * A command stream in TU_CS_MODE_SUB_STREAM mode does not support direct
+ * command packet emission. tu_cs_begin_sub_stream must be called to get a
+ * sub-stream to emit comamnd packets to. When done with the sub-stream,
+ * tu_cs_end_sub_stream must be called.
+ *
+ * This mode does not create any entry internally.
+ */
+ TU_CS_MODE_SUB_STREAM,
+};
+
+struct tu_cs
+{
+ uint32_t *start;
+ uint32_t *cur;
+ uint32_t *reserved_end;
+ uint32_t *end;
+
+ enum tu_cs_mode mode;
+ uint32_t next_bo_size;
+
+ struct tu_cs_entry *entries;
+ uint32_t entry_count;
+ uint32_t entry_capacity;
+
+ struct tu_bo **bos;
+ uint32_t bo_count;
+ uint32_t bo_capacity;
+};
+
struct tu_device_memory
{
struct tu_bo bo;
VkBufferUsageFlags usage;
VkBufferCreateFlags flags;
+
+ struct tu_bo *bo;
+ VkDeviceSize bo_offset;
};
enum tu_dynamic_state_bits
uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
};
+struct tu_tile
+{
+ uint8_t pipe;
+ uint8_t slot;
+ VkOffset2D begin;
+ VkOffset2D end;
+};
+
+struct tu_tiling_config
+{
+ VkRect2D render_area;
+ uint32_t buffer_cpp[MAX_RTS + 2];
+ uint32_t buffer_count;
+
+ /* position and size of the first tile */
+ VkRect2D tile0;
+ /* number of tiles */
+ VkExtent2D tile_count;
+
+ uint32_t gmem_offsets[MAX_RTS + 2];
+
+ /* size of the first VSC pipe */
+ VkExtent2D pipe0;
+ /* number of VSC pipes */
+ VkExtent2D pipe_count;
+
+ /* pipe register values */
+ uint32_t pipe_config[MAX_VSC_PIPES];
+ uint32_t pipe_sizes[MAX_VSC_PIPES];
+};
+
struct tu_cmd_state
{
/* Vertex descriptors */
uint32_t index_type;
uint32_t max_index_count;
uint64_t index_va;
+
+ const struct tu_render_pass *pass;
+ const struct tu_subpass *subpass;
+ const struct tu_framebuffer *framebuffer;
+ struct tu_attachment_state *attachments;
+
+ struct tu_tiling_config tiling_config;
+
+ struct tu_cs_entry tile_load_ib;
+ struct tu_cs_entry tile_store_ib;
};
struct tu_cmd_pool
{
uint32_t count;
uint32_t capacity;
- uint32_t *handles;
+ struct drm_msm_gem_submit_bo *bo_infos;
};
-void tu_bo_list_init(struct tu_bo_list *list);
-void tu_bo_list_destroy(struct tu_bo_list *list);
-void tu_bo_list_reset(struct tu_bo_list *list);
-uint32_t tu_bo_list_add(struct tu_bo_list *list,
- const struct tu_bo *bo);
-
-struct tu_cmd_stream_entry
-{
- /* No ownership */
- struct tu_bo *bo;
-
- uint32_t size;
- uint64_t offset;
-};
-
-struct tu_cmd_stream
-{
- uint32_t *start;
- uint32_t *cur;
- uint32_t *end;
-
- struct tu_cmd_stream_entry *entries;
- uint32_t entry_count;
- uint32_t entry_capacity;
+#define TU_BO_LIST_FAILED (~0)
- struct tu_bo **bos;
- uint32_t bo_count;
- uint32_t bo_capacity;
-};
+void
+tu_bo_list_init(struct tu_bo_list *list);
+void
+tu_bo_list_destroy(struct tu_bo_list *list);
+void
+tu_bo_list_reset(struct tu_bo_list *list);
+uint32_t
+tu_bo_list_add(struct tu_bo_list *list,
+ const struct tu_bo *bo,
+ uint32_t flags);
+VkResult
+tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other);
struct tu_cmd_buffer
{
struct tu_cmd_buffer_upload upload;
+ VkResult record_result;
+
struct tu_bo_list bo_list;
- struct tu_cmd_stream cs;
+ struct tu_cs cs;
+ struct tu_cs draw_cs;
+ struct tu_cs tile_cs;
- VkResult record_result;
+ uint16_t marker_reg;
+ uint32_t marker_seqno;
+
+ struct tu_bo scratch_bo;
+ uint32_t scratch_seqno;
+
+ bool wait_for_idle;
};
+void
+tu6_emit_event_write(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ enum vgt_event_type event,
+ bool need_seqno);
+
bool
tu_get_memory_fd(struct tu_device *device,
struct tu_device_memory *memory,
struct tu_shader_module
{
- struct nir_shader *nir;
unsigned char sha1[20];
- uint32_t size;
- char data[0];
+
+ uint32_t code_size;
+ const uint32_t *code[0];
};
+struct tu_shader_compile_options
+{
+ struct ir3_shader_key key;
+
+ bool optimize;
+ bool include_binning_pass;
+};
+
+struct tu_shader
+{
+ struct ir3_shader ir3_shader;
+
+ /* This may be true for vertex shaders. When true, variants[1] is the
+ * binning variant and binning_binary is non-NULL.
+ */
+ bool has_binning_pass;
+
+ void *binary;
+ void *binning_binary;
+
+ struct ir3_shader_variant variants[0];
+};
+
+struct tu_shader *
+tu_shader_create(struct tu_device *dev,
+ gl_shader_stage stage,
+ const VkPipelineShaderStageCreateInfo *stage_info,
+ const VkAllocationCallbacks *alloc);
+
+void
+tu_shader_destroy(struct tu_device *dev,
+ struct tu_shader *shader,
+ const VkAllocationCallbacks *alloc);
+
+void
+tu_shader_compile_options_init(
+ struct tu_shader_compile_options *options,
+ const VkGraphicsPipelineCreateInfo *pipeline_info);
+
+VkResult
+tu_shader_compile(struct tu_device *dev,
+ struct tu_shader *shader,
+ const struct tu_shader *next_stage,
+ const struct tu_shader_compile_options *options,
+ const VkAllocationCallbacks *alloc);
+
struct tu_pipeline
{
- struct tu_device *device;
+ struct tu_cs cs;
+
struct tu_dynamic_state dynamic_state;
struct tu_pipeline_layout *layout;
bool need_indirect_descriptor_sets;
VkShaderStageFlags active_stages;
+
+ struct
+ {
+ struct tu_bo binary_bo;
+ struct tu_cs_entry state_ib;
+ struct tu_cs_entry binning_state_ib;
+ } program;
+
+ struct
+ {
+ uint8_t bindings[MAX_VERTEX_ATTRIBS];
+ uint16_t strides[MAX_VERTEX_ATTRIBS];
+ uint16_t offsets[MAX_VERTEX_ATTRIBS];
+ uint32_t count;
+
+ uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
+ uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
+ uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
+ uint32_t binning_count;
+
+ struct tu_cs_entry state_ib;
+ struct tu_cs_entry binning_state_ib;
+ } vi;
+
+ struct
+ {
+ enum pc_di_primtype primtype;
+ bool primitive_restart;
+ } ia;
+
+ struct
+ {
+ struct tu_cs_entry state_ib;
+ } vp;
+
+ struct
+ {
+ uint32_t gras_su_cntl;
+ struct tu_cs_entry state_ib;
+ } rast;
+
+ struct
+ {
+ struct tu_cs_entry state_ib;
+ } ds;
+
+ struct
+ {
+ struct tu_cs_entry state_ib;
+ } blend;
};
+void
+tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
+
+void
+tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
+
+void
+tu6_emit_gras_su_cntl(struct tu_cs *cs,
+ uint32_t gras_su_cntl,
+ float line_width);
+
+void
+tu6_emit_depth_bias(struct tu_cs *cs,
+ float constant_factor,
+ float clamp,
+ float slope_factor);
+
+void
+tu6_emit_stencil_compare_mask(struct tu_cs *cs,
+ uint32_t front,
+ uint32_t back);
+
+void
+tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
+
+void
+tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
+
+void
+tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
+
struct tu_userdata_info *
tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
gl_shader_stage stage,
uint32_t custom_blend_mode;
};
-VkResult
-tu_graphics_pipeline_create(
- VkDevice device,
- VkPipelineCache cache,
- const VkGraphicsPipelineCreateInfo *pCreateInfo,
- const struct tu_graphics_pipeline_create_info *extra,
- const VkAllocationCallbacks *alloc,
- VkPipeline *pPipeline);
-
-struct vk_format_description;
-uint32_t
-tu_translate_buffer_dataformat(const struct vk_format_description *desc,
- int first_non_void);
-uint32_t
-tu_translate_buffer_numformat(const struct vk_format_description *desc,
- int first_non_void);
-uint32_t
-tu_translate_colorformat(VkFormat format);
-uint32_t
-tu_translate_color_numformat(VkFormat format,
- const struct vk_format_description *desc,
- int first_non_void);
-uint32_t
-tu_colorformat_endian_swap(uint32_t colorformat);
-unsigned
-tu_translate_colorswap(VkFormat format, bool do_endian_swap);
-uint32_t
-tu_translate_dbformat(VkFormat format);
-uint32_t
-tu_translate_tex_dataformat(VkFormat format,
- const struct vk_format_description *desc,
- int first_non_void);
-uint32_t
-tu_translate_tex_numformat(VkFormat format,
- const struct vk_format_description *desc,
- int first_non_void);
-bool
-tu_format_pack_clear_color(VkFormat format,
- uint32_t clear_vals[2],
- VkClearColorValue *value);
-bool
-tu_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
-bool
-tu_dcc_formats_compatible(VkFormat format1, VkFormat format2);
+struct tu_native_format
+{
+ int vtx; /* VFMTn_xxx or -1 */
+ int tex; /* TFMTn_xxx or -1 */
+ int rb; /* RBn_xxx or -1 */
+ int swap; /* enum a3xx_color_swap */
+ bool present; /* internal only; always true to external users */
+};
+
+const struct tu_native_format *
+tu6_get_native_format(VkFormat format);
+
+int
+tu_pack_clear_value(const VkClearValue *val,
+ VkFormat format,
+ uint32_t buf[4]);
+enum a6xx_2d_ifmt tu6_rb_fmt_to_ifmt(enum a6xx_color_fmt fmt);
struct tu_image_level
{
VkImageTiling tiling; /** VkImageCreateInfo::tiling */
VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
VkExtent3D extent;
+ uint32_t level_count;
+ uint32_t layer_count;
VkDeviceSize size;
uint32_t alignment;
/* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
VkDeviceMemory owned_memory;
+
+ /* Set when bound */
+ const struct tu_bo *bo;
+ VkDeviceSize bo_offset;
};
unsigned
tu_get_layerCount(const struct tu_image *image,
const VkImageSubresourceRange *range)
{
- abort();
+ return range->layerCount == VK_REMAINING_ARRAY_LAYERS
+ ? image->layer_count - range->baseArrayLayer
+ : range->layerCount;
}
static inline uint32_t
tu_get_levelCount(const struct tu_image *image,
const VkImageSubresourceRange *range)
{
- abort();
+ return range->levelCount == VK_REMAINING_MIP_LEVELS
+ ? image->level_count - range->baseMipLevel
+ : range->levelCount;
}
struct tu_image_view
uint32_t descriptorWriteCount,
const VkWriteDescriptorSet *pDescriptorWrites);
-struct tu_fence
-{
- uint32_t syncobj;
- uint32_t temp_syncobj;
-};
+int
+tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id);
+
+int
+tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size);
+
+int
+tu_drm_submitqueue_new(const struct tu_device *dev,
+ int priority,
+ uint32_t *queue_id);
+void
+tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id);
+
+uint32_t
+tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags);
uint32_t
-tu_gem_new(struct tu_device *dev, uint64_t size, uint32_t flags);
+tu_gem_import_dmabuf(const struct tu_device *dev,
+ int prime_fd,
+ uint64_t size);
+int
+tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle);
void
-tu_gem_close(struct tu_device *dev, uint32_t gem_handle);
+tu_gem_close(const struct tu_device *dev, uint32_t gem_handle);
uint64_t
-tu_gem_info_offset(struct tu_device *dev, uint32_t gem_handle);
+tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle);
uint64_t
-tu_gem_info_iova(struct tu_device *dev, uint32_t gem_handle);
-int
-tu_drm_query_param(struct tu_physical_device *dev,
- uint32_t param,
- uint64_t *value);
+tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle);
#define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \
\
projects / mesa.git / blobdiff