turnip: add draw_cs to tu_cmd_buffer
[mesa.git] / src / freedreno / vulkan / tu_private.h
index c64d4ce49571092abb3f0ee4504b5e1136812e49..b9f7deec0a1328dbbf2a099dbbd468efd9214c38 100644 (file)
 #include "vk_debug_report.h"
 
 #include "drm/msm_drm.h"
+#include "ir3/ir3_compiler.h"
+#include "ir3/ir3_shader.h"
+
+#include "adreno_common.xml.h"
+#include "adreno_pm4.xml.h"
+#include "a6xx.xml.h"
+
 #include "tu_descriptor_set.h"
 #include "tu_extensions.h"
 
@@ -73,7 +80,7 @@ typedef uint32_t xcb_window_t;
 #define MAX_VERTEX_ATTRIBS 32
 #define MAX_RTS 8
 #define MAX_VSC_PIPES 32
-#define MAX_VIEWPORTS 16
+#define MAX_VIEWPORTS 1
 #define MAX_SCISSORS 16
 #define MAX_DISCARD_RECTANGLES 4
 #define MAX_PUSH_CONSTANTS_SIZE 128
@@ -310,6 +317,8 @@ struct tu_physical_device
 enum tu_debug_flags
 {
    TU_DEBUG_STARTUP = 1 << 0,
+   TU_DEBUG_NIR = 1 << 1,
+   TU_DEBUG_IR3 = 1 << 2,
 };
 
 struct tu_instance
@@ -442,6 +451,8 @@ struct tu_device
 
    struct tu_physical_device *physical_device;
 
+   struct ir3_compiler *compiler;
+
    /* Backup in-memory cache to be used if the app doesn't provide one */
    struct tu_pipeline_cache *mem_cache;
 
@@ -479,7 +490,7 @@ struct tu_cs_entry
    const struct tu_bo *bo;
 
    uint32_t size;
-   uint64_t offset;
+   uint32_t offset;
 };
 
 enum tu_cs_mode
@@ -890,6 +901,7 @@ struct tu_cmd_buffer
 
    struct tu_bo_list bo_list;
    struct tu_cs cs;
+   struct tu_cs draw_cs;
    struct tu_cs tile_cs;
 
    uint16_t marker_reg;
@@ -901,6 +913,12 @@ struct tu_cmd_buffer
    bool wait_for_idle;
 };
 
+void
+tu6_emit_event_write(struct tu_cmd_buffer *cmd,
+                     struct tu_cs *cs,
+                     enum vgt_event_type event,
+                     bool need_seqno);
+
 bool
 tu_get_memory_fd(struct tu_device *device,
                  struct tu_device_memory *memory,
@@ -958,23 +976,151 @@ mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
 
 struct tu_shader_module
 {
-   struct nir_shader *nir;
    unsigned char sha1[20];
-   uint32_t size;
-   char data[0];
+
+   uint32_t code_size;
+   const uint32_t *code[0];
+};
+
+struct tu_shader_compile_options
+{
+   struct ir3_shader_key key;
+
+   bool optimize;
+   bool include_binning_pass;
 };
 
+struct tu_shader
+{
+   struct ir3_shader ir3_shader;
+
+   /* This may be true for vertex shaders.  When true, variants[1] is the
+    * binning variant and binning_binary is non-NULL.
+    */
+   bool has_binning_pass;
+
+   void *binary;
+   void *binning_binary;
+
+   struct ir3_shader_variant variants[0];
+};
+
+struct tu_shader *
+tu_shader_create(struct tu_device *dev,
+                 gl_shader_stage stage,
+                 const VkPipelineShaderStageCreateInfo *stage_info,
+                 const VkAllocationCallbacks *alloc);
+
+void
+tu_shader_destroy(struct tu_device *dev,
+                  struct tu_shader *shader,
+                  const VkAllocationCallbacks *alloc);
+
+void
+tu_shader_compile_options_init(
+   struct tu_shader_compile_options *options,
+   const VkGraphicsPipelineCreateInfo *pipeline_info);
+
+VkResult
+tu_shader_compile(struct tu_device *dev,
+                  struct tu_shader *shader,
+                  const struct tu_shader *next_stage,
+                  const struct tu_shader_compile_options *options,
+                  const VkAllocationCallbacks *alloc);
+
 struct tu_pipeline
 {
-   struct tu_device *device;
+   struct tu_cs cs;
+
    struct tu_dynamic_state dynamic_state;
 
    struct tu_pipeline_layout *layout;
 
    bool need_indirect_descriptor_sets;
    VkShaderStageFlags active_stages;
+
+   struct
+   {
+      struct tu_bo binary_bo;
+      struct tu_cs_entry state_ib;
+      struct tu_cs_entry binning_state_ib;
+   } program;
+
+   struct
+   {
+      uint8_t bindings[MAX_VERTEX_ATTRIBS];
+      uint16_t strides[MAX_VERTEX_ATTRIBS];
+      uint16_t offsets[MAX_VERTEX_ATTRIBS];
+      uint32_t count;
+
+      uint8_t binning_bindings[MAX_VERTEX_ATTRIBS];
+      uint16_t binning_strides[MAX_VERTEX_ATTRIBS];
+      uint16_t binning_offsets[MAX_VERTEX_ATTRIBS];
+      uint32_t binning_count;
+
+      struct tu_cs_entry state_ib;
+      struct tu_cs_entry binning_state_ib;
+   } vi;
+
+   struct
+   {
+      enum pc_di_primtype primtype;
+      bool primitive_restart;
+   } ia;
+
+   struct
+   {
+      struct tu_cs_entry state_ib;
+   } vp;
+
+   struct
+   {
+      uint32_t gras_su_cntl;
+      struct tu_cs_entry state_ib;
+   } rast;
+
+   struct
+   {
+      struct tu_cs_entry state_ib;
+   } ds;
+
+   struct
+   {
+      struct tu_cs_entry state_ib;
+   } blend;
 };
 
+void
+tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport);
+
+void
+tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor);
+
+void
+tu6_emit_gras_su_cntl(struct tu_cs *cs,
+                      uint32_t gras_su_cntl,
+                      float line_width);
+
+void
+tu6_emit_depth_bias(struct tu_cs *cs,
+                    float constant_factor,
+                    float clamp,
+                    float slope_factor);
+
+void
+tu6_emit_stencil_compare_mask(struct tu_cs *cs,
+                              uint32_t front,
+                              uint32_t back);
+
+void
+tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back);
+
+void
+tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back);
+
+void
+tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4]);
+
 struct tu_userdata_info *
 tu_lookup_user_sgpr(struct tu_pipeline *pipeline,
                     gl_shader_stage stage,
@@ -996,15 +1142,6 @@ struct tu_graphics_pipeline_create_info
    uint32_t custom_blend_mode;
 };
 
-VkResult
-tu_graphics_pipeline_create(
-   VkDevice device,
-   VkPipelineCache cache,
-   const VkGraphicsPipelineCreateInfo *pCreateInfo,
-   const struct tu_graphics_pipeline_create_info *extra,
-   const VkAllocationCallbacks *alloc,
-   VkPipeline *pPipeline);
-
 struct tu_native_format
 {
    int vtx;      /* VFMTn_xxx or -1 */
@@ -1021,6 +1158,7 @@ int
 tu_pack_clear_value(const VkClearValue *val,
                     VkFormat format,
                     uint32_t buf[4]);
+enum a6xx_2d_ifmt tu6_rb_fmt_to_ifmt(enum a6xx_color_fmt fmt);
 
 struct tu_image_level
 {