#include "adreno_common.xml.h"
#include "adreno_pm4.xml.h"
#include "a6xx.xml.h"
+#include "fdl/freedreno_layout.h"
#include "tu_descriptor_set.h"
#include "tu_extensions.h"
#define MAX_VIEWS 8
/* The Qualcomm driver exposes 0x20000058 */
#define MAX_STORAGE_BUFFER_RANGE 0x20000000
+/* TODO: this isn't a hardware limit, but for a high # of attachments
+ * we are missing logic to avoid having them all in GMEM at the same time
+ */
+#define MAX_ATTACHMENTS 64
#define NUM_DEPTH_CLEAR_PIPELINES 3
TU_DEBUG_STARTUP = 1 << 0,
TU_DEBUG_NIR = 1 << 1,
TU_DEBUG_IR3 = 1 << 2,
+ TU_DEBUG_NOBIN = 1 << 3,
};
struct tu_instance
uint32_t offset;
};
+struct ts_cs_memory {
+ uint32_t *map;
+ uint64_t iova;
+};
+
enum tu_cs_mode
{
VkDeviceSize bo_offset;
};
+static inline uint64_t
+tu_buffer_iova(struct tu_buffer *buffer)
+{
+ return buffer->bo->iova + buffer->bo_offset;
+}
+
enum tu_dynamic_state_bits
{
TU_DYNAMIC_VIEWPORT = 1 << 0,
const char *
tu_get_perftest_option_name(int id);
-/**
- * Attachment state when recording a renderpass instance.
- *
- * The clear value is valid only if there exists a pending clear.
- */
-struct tu_attachment_state
-{
- VkImageAspectFlags pending_clear_aspects;
- uint32_t cleared_views;
- VkClearValue clear_value;
- VkImageLayout current_layout;
-};
-
struct tu_descriptor_state
{
struct tu_descriptor_set *sets[MAX_SETS];
struct tu_tiling_config
{
VkRect2D render_area;
- uint32_t buffer_cpp[MAX_RTS + 2];
+ uint32_t buffer_cpp[MAX_ATTACHMENTS];
uint32_t buffer_count;
/* position and size of the first tile */
/* number of tiles */
VkExtent2D tile_count;
- uint32_t gmem_offsets[MAX_RTS + 2];
+ uint32_t gmem_offsets[MAX_ATTACHMENTS];
/* size of the first VSC pipe */
VkExtent2D pipe0;
enum tu_cmd_dirty_bits
{
TU_CMD_DIRTY_PIPELINE = 1 << 0,
- TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 1,
- TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 2,
+ TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1,
+ TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2,
+ TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
+ TU_CMD_DIRTY_PUSH_CONSTANTS = 1 << 4,
TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 16,
TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 17,
uint32_t dirty;
struct tu_pipeline *pipeline;
+ struct tu_pipeline *compute_pipeline;
/* Vertex buffers */
struct
const struct tu_render_pass *pass;
const struct tu_subpass *subpass;
const struct tu_framebuffer *framebuffer;
- struct tu_attachment_state *attachments;
struct tu_tiling_config tiling_config;
struct tu_bo scratch_bo;
uint32_t scratch_seqno;
+#define VSC_OVERFLOW 0x8
+#define VSC_SCRATCH 0x10
+
+ struct tu_bo vsc_data;
+ struct tu_bo vsc_data2;
+ uint32_t vsc_data_pitch;
+ uint32_t vsc_data2_pitch;
+ bool use_vsc_data;
bool wait_for_idle;
};
-void
+unsigned
tu6_emit_event_write(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
enum vgt_event_type event,
unsigned num;
int set[64];
int binding[64];
+ int value[64];
};
struct tu_shader
{
struct tu_cs_entry state_ib;
} blend;
+
+ struct
+ {
+ uint32_t local_size[3];
+ } compute;
};
void
VkSampleCountFlagBits samples;
- VkDeviceSize size;
uint32_t alignment;
- /* memory layout */
- VkDeviceSize layer_size;
- struct tu_image_level levels[15];
- unsigned tile_mode;
- unsigned cpp;
- struct tu_image_level ubwc_levels[15];
- uint32_t ubwc_size;
+ struct fdl_layout layout;
unsigned queue_family_mask;
bool exclusive;
static inline VkDeviceSize
tu_layer_size(struct tu_image *image, int level)
{
- if (image->type == VK_IMAGE_TYPE_3D)
- return image->levels[level].size;
- return image->layer_size;
+ return fdl_layer_stride(&image->layout, level);
}
static inline uint32_t
tu_image_stride(struct tu_image *image, int level)
{
- return image->levels[level].pitch * image->cpp;
+ return image->layout.slices[level].pitch * image->layout.cpp;
}
static inline uint64_t
tu_image_base(struct tu_image *image, int level, int layer)
{
- return image->bo->iova + image->bo_offset + image->levels[level].offset +
- layer * tu_layer_size(image, level);
+ return image->bo->iova + image->bo_offset +
+ fdl_surface_offset(&image->layout, level, layer);
}
static inline VkDeviceSize
tu_image_ubwc_size(struct tu_image *image, int level)
{
- return image->ubwc_size;
+ return image->layout.ubwc_size;
}
static inline uint32_t
tu_image_ubwc_pitch(struct tu_image *image, int level)
{
- return image->ubwc_levels[level].pitch;
+ return image->layout.ubwc_slices[level].pitch;
}
static inline uint64_t
tu_image_ubwc_base(struct tu_image *image, int level, int layer)
{
- return image->bo->iova + image->bo_offset + image->ubwc_levels[level].offset +
+ return image->bo->iova + image->bo_offset +
+ image->layout.ubwc_slices[level].offset +
layer * tu_image_ubwc_size(image, level);
}
uint32_t state[A6XX_TEX_SAMP_DWORDS];
bool needs_border;
+ VkBorderColor border;
};
VkResult
struct tu_attachment_info attachments[0];
};
-struct tu_subpass_barrier
-{
- VkPipelineStageFlags src_stage_mask;
- VkAccessFlags src_access_mask;
- VkAccessFlags dst_access_mask;
-};
-
-void
-tu_subpass_barrier(struct tu_cmd_buffer *cmd_buffer,
- const struct tu_subpass_barrier *barrier);
-
struct tu_subpass_attachment
{
uint32_t attachment;
- VkImageLayout layout;
};
struct tu_subpass
struct tu_subpass_attachment *resolve_attachments;
struct tu_subpass_attachment depth_stencil_attachment;
- struct tu_subpass_barrier start_barrier;
-
- uint32_t view_mask;
- VkSampleCountFlagBits max_sample_count;
+ VkSampleCountFlagBits samples;
};
struct tu_render_pass_attachment
{
VkFormat format;
- uint32_t samples;
+ uint32_t cpp;
VkAttachmentLoadOp load_op;
VkAttachmentLoadOp stencil_load_op;
- VkImageLayout initial_layout;
- VkImageLayout final_layout;
- uint32_t view_mask;
+ VkAttachmentStoreOp store_op;
+ VkAttachmentStoreOp stencil_store_op;
+ bool needs_gmem;
};
struct tu_render_pass
uint32_t subpass_count;
struct tu_subpass_attachment *subpass_attachments;
struct tu_render_pass_attachment *attachments;
- struct tu_subpass_barrier end_barrier;
struct tu_subpass subpasses[0];
};
projects / mesa.git / blobdiff