#include "tu_descriptor_set.h"
#include "tu_extensions.h"
+#include "tu_util.h"
/* Pre-declarations needed for WSI entrypoints */
struct wl_surface;
uint32_t offset;
};
-struct ts_cs_memory {
+struct tu_cs_memory {
uint32_t *map;
uint64_t iova;
};
{
TU_DRAW_STATE_PROGRAM,
TU_DRAW_STATE_PROGRAM_BINNING,
+ TU_DRAW_STATE_TESS,
TU_DRAW_STATE_VB,
TU_DRAW_STATE_VI,
TU_DRAW_STATE_VI_BINNING,
TU_DRAW_STATE_DS,
TU_DRAW_STATE_BLEND,
TU_DRAW_STATE_VS_CONST,
+ TU_DRAW_STATE_HS_CONST,
+ TU_DRAW_STATE_DS_CONST,
TU_DRAW_STATE_GS_CONST,
TU_DRAW_STATE_FS_CONST,
TU_DRAW_STATE_DESC_SETS,
TU_DRAW_STATE_DESC_SETS_LOAD,
TU_DRAW_STATE_VS_PARAMS,
+ TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
+ TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
/* dynamic state related draw states */
TU_DRAW_STATE_DYNAMIC,
TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
TU_CMD_DIRTY_SHADER_CONSTS = 1 << 5,
- TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
/* all draw states were disabled and need to be re-enabled: */
TU_CMD_DIRTY_DRAW_STATE = 1 << 7,
};
-struct tu_streamout_state {
- uint16_t stride[IR3_MAX_SO_BUFFERS];
- uint32_t ncomp[IR3_MAX_SO_BUFFERS];
- uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
- uint32_t prog_count;
- uint32_t vpc_so_buf_cntl;
-};
-
/* There are only three cache domains we have to care about: the CCU, or
* color cache unit, which is used for color and depth/stencil attachments
* and copy/blit destinations, and is split conceptually into color and depth,
struct tu_cs_entry vertex_buffers_ib;
struct tu_cs_entry shader_const_ib[MESA_SHADER_STAGES];
struct tu_cs_entry desc_sets_ib, desc_sets_load_ib;
-
- /* Stream output buffers */
- struct
- {
- struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
- VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
- VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
- } streamout_buf;
-
- uint8_t streamout_reset;
- uint8_t streamout_enabled;
+ struct tu_cs_entry ia_gmem_ib, ia_sysmem_ib;
/* Index buffer */
- struct tu_buffer *index_buffer;
- uint64_t index_offset;
- uint32_t index_type;
- uint32_t max_index_count;
uint64_t index_va;
+ uint32_t max_index_count;
+ uint8_t index_size, index_shift;
+
+ /* because streamout base has to be 32-byte aligned
+ * there is an extra offset to deal with when it is
+ * unaligned
+ */
+ uint8_t streamout_offset[IR3_MAX_SO_BUFFERS];
/* Renderpasses are tricky, because we may need to flush differently if
* using sysmem vs. gmem and therefore we have to delay any flushing that
struct tu_tiling_config tiling_config;
struct tu_cs_entry tile_store_ib;
+
+ bool xfb_used;
};
struct tu_cmd_pool
struct tu_bo scratch_bo;
+ bool has_tess;
+
struct tu_bo vsc_draw_strm;
struct tu_bo vsc_prim_strm;
uint32_t vsc_draw_strm_pitch;
struct tu_bo bo;
};
-static inline gl_shader_stage
-vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
-{
- assert(__builtin_popcount(vk_stage) == 1);
- return ffs(vk_stage) - 1;
-}
-
-static inline VkShaderStageFlagBits
-mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
-{
- return (1 << mesa_stage);
-}
-
-#define TU_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
-
-#define tu_foreach_stage(stage, stage_bits) \
- for (gl_shader_stage stage, \
- __tmp = (gl_shader_stage)((stage_bits) &TU_STAGE_MASK); \
- stage = __builtin_ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
-
-uint32_t
-tu6_stage2opcode(gl_shader_stage type);
-enum a6xx_state_block
-tu6_stage2shadersb(gl_shader_stage type);
-
struct tu_shader_module
{
unsigned char sha1[20];
struct tu_program_descriptor_linkage
{
- struct ir3_ubo_analysis_state ubo_state;
struct ir3_const_state const_state;
uint32_t constlen;
VkShaderStageFlags active_stages;
uint32_t active_desc_sets;
- struct tu_streamout_state streamout;
-
/* mask of enabled dynamic states
* if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
*/
struct
{
- struct tu_bo binary_bo;
struct tu_cs_entry state_ib;
struct tu_cs_entry binning_state_ib;
bool primitive_restart;
} ia;
+ struct
+ {
+ uint32_t patch_type;
+ uint32_t per_vertex_output_size;
+ uint32_t per_patch_output_size;
+ uint32_t hs_bo_regid;
+ uint32_t ds_bo_regid;
+ bool upper_left_domain_origin;
+ } tess;
+
struct
{
struct tu_cs_entry state_ib;
void
tu6_emit_vpc(struct tu_cs *cs,
const struct ir3_shader_variant *vs,
+ const struct ir3_shader_variant *hs,
+ const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
- const struct ir3_shader_variant *fs,
- struct tu_streamout_state *tf);
+ const struct ir3_shader_variant *fs);
void
tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
return tu6_format_color(format, TILE6_LINEAR).fmt;
}
-enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
-
struct tu_image
{
VkImageType type;
: range->levelCount;
}
-enum a3xx_msaa_samples
-tu_msaa_samples(uint32_t samples);
-enum a6xx_tex_fetchsize
-tu6_fetchsize(VkFormat format);
-
struct tu_image_view
{
struct tu_image *image; /**< VkImageViewCreateInfo::image */
void
tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer);
-enum a6xx_tex_filter
-tu6_tex_filter(VkFilter filter, unsigned aniso);
-
VkResult
tu_image_create(VkDevice _device,
const VkImageCreateInfo *pCreateInfo,
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