freedreno/registers: a6xx depth bounds test registers

[mesa.git] / src / freedreno / vulkan / tu_private.h

diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h
index 39f303ee7d7c596787bcc169316a161e9e094a9a..fea76539c2a2fb1588eda18885301a8ee71df01f 100644 (file)
--- a/src/freedreno/vulkan/tu_private.h
+++ b/src/freedreno/vulkan/tu_private.h
@@ -406,7 +406,7 @@ struct tu_cs_entry
    uint32_t offset;
 };
 
-struct ts_cs_memory {
+struct tu_cs_memory {
    uint32_t *map;
    uint64_t iova;
 };
@@ -427,6 +427,7 @@ enum tu_draw_state_group_id
 {
    TU_DRAW_STATE_PROGRAM,
    TU_DRAW_STATE_PROGRAM_BINNING,
+   TU_DRAW_STATE_TESS,
    TU_DRAW_STATE_VB,
    TU_DRAW_STATE_VI,
    TU_DRAW_STATE_VI_BINNING,
@@ -434,6 +435,8 @@ enum tu_draw_state_group_id
    TU_DRAW_STATE_DS,
    TU_DRAW_STATE_BLEND,
    TU_DRAW_STATE_VS_CONST,
+   TU_DRAW_STATE_HS_CONST,
+   TU_DRAW_STATE_DS_CONST,
    TU_DRAW_STATE_GS_CONST,
    TU_DRAW_STATE_FS_CONST,
    TU_DRAW_STATE_DESC_SETS,
@@ -671,19 +674,10 @@ enum tu_cmd_dirty_bits
    TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3,
    TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4,
    TU_CMD_DIRTY_SHADER_CONSTS = 1 << 5,
-   TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6,
    /* all draw states were disabled and need to be re-enabled: */
    TU_CMD_DIRTY_DRAW_STATE = 1 << 7,
 };
 
-struct tu_streamout_state {
-   uint16_t stride[IR3_MAX_SO_BUFFERS];
-   uint32_t ncomp[IR3_MAX_SO_BUFFERS];
-   uint32_t prog[IR3_MAX_SO_OUTPUTS * 2];
-   uint32_t prog_count;
-   uint32_t vpc_so_buf_cntl;
-};
-
 /* There are only three cache domains we have to care about: the CCU, or
  * color cache unit, which is used for color and depth/stencil attachments
  * and copy/blit destinations, and is split conceptually into color and depth,
@@ -821,23 +815,16 @@ struct tu_cmd_state
    struct tu_cs_entry desc_sets_ib, desc_sets_load_ib;
    struct tu_cs_entry ia_gmem_ib, ia_sysmem_ib;
 
-   /* Stream output buffers */
-   struct
-   {
-      struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS];
-      VkDeviceSize offsets[IR3_MAX_SO_BUFFERS];
-      VkDeviceSize sizes[IR3_MAX_SO_BUFFERS];
-   } streamout_buf;
-
-   uint8_t streamout_reset;
-   uint8_t streamout_enabled;
-
    /* Index buffer */
-   struct tu_buffer *index_buffer;
-   uint64_t index_offset;
-   uint32_t index_type;
-   uint32_t max_index_count;
    uint64_t index_va;
+   uint32_t max_index_count;
+   uint8_t index_size, index_shift;
+
+   /* because streamout base has to be 32-byte aligned
+    * there is an extra offset to deal with when it is
+    * unaligned
+    */
+   uint8_t streamout_offset[IR3_MAX_SO_BUFFERS];
 
    /* Renderpasses are tricky, because we may need to flush differently if
     * using sysmem vs. gmem and therefore we have to delay any flushing that
@@ -857,6 +844,8 @@ struct tu_cmd_state
    struct tu_tiling_config tiling_config;
 
    struct tu_cs_entry tile_store_ib;
+
+   bool xfb_used;
 };
 
 struct tu_cmd_pool
@@ -964,6 +953,8 @@ struct tu_cmd_buffer
 
    struct tu_bo scratch_bo;
 
+   bool has_tess;
+
    struct tu_bo vsc_draw_strm;
    struct tu_bo vsc_prim_strm;
    uint32_t vsc_draw_strm_pitch;
@@ -1062,8 +1053,6 @@ struct tu_pipeline
    VkShaderStageFlags active_stages;
    uint32_t active_desc_sets;
 
-   struct tu_streamout_state streamout;
-
    /* mask of enabled dynamic states
     * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used
     */
@@ -1075,7 +1064,6 @@ struct tu_pipeline
 
    struct
    {
-      struct tu_bo binary_bo;
       struct tu_cs_entry state_ib;
       struct tu_cs_entry binning_state_ib;
 
@@ -1100,6 +1088,16 @@ struct tu_pipeline
       bool primitive_restart;
    } ia;
 
+   struct
+   {
+      uint32_t patch_type;
+      uint32_t per_vertex_output_size;
+      uint32_t per_patch_output_size;
+      uint32_t hs_bo_regid;
+      uint32_t ds_bo_regid;
+      bool upper_left_domain_origin;
+   } tess;
+
    struct
    {
       struct tu_cs_entry state_ib;
@@ -1151,9 +1149,10 @@ tu6_emit_xs_config(struct tu_cs *cs,
 void
 tu6_emit_vpc(struct tu_cs *cs,
              const struct ir3_shader_variant *vs,
+             const struct ir3_shader_variant *hs,
+             const struct ir3_shader_variant *ds,
              const struct ir3_shader_variant *gs,
-             const struct ir3_shader_variant *fs,
-             struct tu_streamout_state *tf);
+             const struct ir3_shader_variant *fs);
 
 void
 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);