const struct spirv_to_nir_options spirv_options = {
.frag_coord_is_sysval = true,
.lower_ubo_ssbo_access_to_offsets = true,
+ .tess_levels_are_sysvals = true,
+ .lower_tess_levels_to_vec = true,
.caps = {
- .transform_feedback = compiler->gpu_id >= 600,
+ .transform_feedback = true,
+ .tessellation = true,
},
};
const nir_shader_compiler_options *nir_options =
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
base = layout->set[set].dynamic_offset_start +
- binding_layout->dynamic_offset_offset +
- layout->input_attachment_count;
+ binding_layout->dynamic_offset_offset;
set = MAX_SETS;
break;
default:
nir_intrinsic_instr *bindless =
nir_intrinsic_instr_create(b->shader,
nir_intrinsic_bindless_resource_ir3);
- bindless->num_components = 1;
+ bindless->num_components = 0;
nir_ssa_dest_init(&bindless->instr, &bindless->dest,
1, 32, NULL);
nir_intrinsic_set_desc_set(bindless, set);
const struct tu_descriptor_set_binding_layout *bind_layout =
&layout->set[set].layout->binding[binding];
+ /* input attachments use non bindless workaround */
+ if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
+ const struct glsl_type *glsl_type = glsl_without_array(var->type);
+ uint32_t idx = var->data.index * 2;
+
+ b->shader->info.textures_used |=
+ ((1ull << (bind_layout->array_size * 2)) - 1) << (idx * 2);
+
+ /* D24S8 workaround: stencil of D24S8 will be sampled as uint */
+ if (glsl_get_sampler_result_type(glsl_type) == GLSL_TYPE_UINT)
+ idx += 1;
+
+ if (deref->deref_type == nir_deref_type_var)
+ return nir_imm_int(b, idx);
+
+ nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
+ return nir_iadd(b, nir_imm_int(b, idx),
+ nir_imul_imm(b, arr_index, 2));
+ }
+
shader->active_desc_sets |= 1u << set;
nir_ssa_def *desc_offset;
unsigned descriptor_stride;
- if (bind_layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
- unsigned offset =
- layout->set[set].input_attachment_start +
- bind_layout->input_attachment_offset;
- desc_offset = nir_imm_int(b, offset);
- set = MAX_SETS;
- descriptor_stride = 1;
- } else {
- unsigned offset = 0;
- /* Samplers come second in combined image/sampler descriptors, see
- * write_combined_image_sampler_descriptor().
- */
- if (is_sampler && bind_layout->type ==
- VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
- offset = 1;
- }
- desc_offset =
- nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
- offset);
- descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
+ unsigned offset = 0;
+ /* Samplers come second in combined image/sampler descriptors, see
+ * write_combined_image_sampler_descriptor().
+ */
+ if (is_sampler && bind_layout->type ==
+ VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
+ offset = 1;
}
+ desc_offset =
+ nir_imm_int(b, (bind_layout->offset / (4 * A6XX_TEX_CONST_DWORDS)) +
+ offset);
+ descriptor_stride = bind_layout->size / (4 * A6XX_TEX_CONST_DWORDS);
if (deref->deref_type != nir_deref_type_var) {
assert(deref->deref_type == nir_deref_type_array);
nir_intrinsic_instr *bindless =
nir_intrinsic_instr_create(b->shader,
nir_intrinsic_bindless_resource_ir3);
- bindless->num_components = 1;
+ bindless->num_components = 0;
nir_ssa_dest_init(&bindless->instr, &bindless->dest,
1, 32, NULL);
nir_intrinsic_set_desc_set(bindless, set);
nir_instr_rewrite_src(&tex->instr, &tex->src[tex_src_idx].src,
nir_src_for_ssa(bindless));
tex->src[tex_src_idx].src_type = nir_tex_src_texture_handle;
+
+ /* for the input attachment case: */
+ if (bindless->parent_instr->type != nir_instr_type_intrinsic)
+ tex->src[tex_src_idx].src_type = nir_tex_src_texture_offset;
}
return true;
if (min >= max) {
tu_shader->push_consts.lo = 0;
tu_shader->push_consts.count = 0;
- tu_shader->ir3_shader.const_state.num_reserved_user_consts = 0;
return;
}
tu_shader->push_consts.lo = (min / 16) / 4 * 4;
tu_shader->push_consts.count =
align(max, 16) / 16 - tu_shader->push_consts.lo;
- tu_shader->ir3_shader.const_state.num_reserved_user_consts =
- align(tu_shader->push_consts.count, 4);
-}
-
-/* Gather the InputAttachmentIndex for each input attachment from the NIR
- * shader and organize the info in a way so that draw-time patching is easy.
- */
-static void
-gather_input_attachments(nir_shader *shader, struct tu_shader *tu_shader,
- const struct tu_pipeline_layout *layout)
-{
- nir_foreach_variable(var, &shader->uniforms) {
- const struct glsl_type *glsl_type = glsl_without_array(var->type);
-
- if (!glsl_type_is_image(glsl_type))
- continue;
-
- enum glsl_sampler_dim dim = glsl_get_sampler_dim(glsl_type);
-
- const uint32_t set = var->data.descriptor_set;
- const uint32_t binding = var->data.binding;
- const struct tu_descriptor_set_binding_layout *bind_layout =
- &layout->set[set].layout->binding[binding];
- const uint32_t array_size = bind_layout->array_size;
-
- if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
- dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
- unsigned offset =
- layout->set[set].input_attachment_start +
- bind_layout->input_attachment_offset;
- for (unsigned i = 0; i < array_size; i++)
- tu_shader->attachment_idx[offset + i] = var->data.index + i;
- }
- }
}
static bool
bool progress = false;
gather_push_constants(shader, tu_shader);
- gather_input_attachments(shader, tu_shader, layout);
nir_foreach_function(function, shader) {
if (function->impl)
progress |= lower_impl(function->impl, tu_shader, layout);
}
+ /* Remove now-unused variables so that when we gather the shader info later
+ * they won't be counted.
+ */
+
+ if (progress)
+ nir_opt_dce(shader);
+
+ progress |=
+ nir_remove_dead_variables(shader,
+ nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo,
+ NULL);
+
return progress;
}
static void
-tu_gather_xfb_info(nir_shader *nir, struct tu_shader *shader)
+tu_gather_xfb_info(nir_shader *nir, struct ir3_stream_output_info *info)
{
- struct ir3_stream_output_info *info = &shader->ir3_shader.stream_output;
nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
if (!xfb)
{
struct tu_shader *shader;
- const uint32_t max_variant_count = (stage == MESA_SHADER_VERTEX) ? 2 : 1;
shader = vk_zalloc2(
&dev->alloc, alloc,
- sizeof(*shader) + sizeof(struct ir3_shader_variant) * max_variant_count,
+ sizeof(*shader),
8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
if (!shader)
return NULL;
* Also needs to be called after nir_remove_dead_variables with varyings,
* so that we could align stream outputs correctly.
*/
+ struct ir3_stream_output_info so_info = {};
if (nir->info.stage == MESA_SHADER_VERTEX ||
nir->info.stage == MESA_SHADER_TESS_EVAL ||
nir->info.stage == MESA_SHADER_GEOMETRY)
- tu_gather_xfb_info(nir, shader);
+ tu_gather_xfb_info(nir, &so_info);
NIR_PASS_V(nir, nir_propagate_invariant);
NIR_PASS_V(nir, nir_opt_combine_stores, nir_var_all);
/* ir3 doesn't support indirect input/output */
+ /* TODO: We shouldn't perform this lowering pass on gl_TessLevelInner
+ * and gl_TessLevelOuter. Since the tess levels are actually stored in
+ * a global BO, they can be directly accessed via stg and ldg.
+ * nir_lower_indirect_derefs will instead generate a big if-ladder which
+ * isn't *incorrect* but is much less efficient. */
NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out);
NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
if (stage == MESA_SHADER_FRAGMENT)
NIR_PASS_V(nir, nir_lower_input_attachments, true);
- if (stage == MESA_SHADER_GEOMETRY)
- NIR_PASS_V(nir, ir3_nir_lower_gs);
-
NIR_PASS_V(nir, tu_lower_io, shader, layout);
- NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
-
- if (stage == MESA_SHADER_FRAGMENT) {
- /* NOTE: lower load_barycentric_at_sample first, since it
- * produces load_barycentric_at_offset:
- */
- NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
- NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
-
- NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
- }
-
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
- /* num_uniforms only used by ir3 for size of ubo 0 (push constants) */
- nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE / 16;
-
- shader->ir3_shader.compiler = dev->compiler;
- shader->ir3_shader.type = stage;
- shader->ir3_shader.nir = nir;
+ shader->ir3_shader =
+ ir3_shader_from_nir(dev->compiler, nir,
+ align(shader->push_consts.count, 4),
+ &so_info);
return shader;
}
struct tu_shader *shader,
const VkAllocationCallbacks *alloc)
{
- if (shader->ir3_shader.nir)
- ralloc_free(shader->ir3_shader.nir);
-
- for (uint32_t i = 0; i < 1 + shader->has_binning_pass; i++) {
- if (shader->variants[i].ir)
- ir3_destroy(shader->variants[i].ir);
- }
-
- if (shader->ir3_shader.const_state.immediates)
- free(shader->ir3_shader.const_state.immediates);
- if (shader->binary)
- free(shader->binary);
- if (shader->binning_binary)
- free(shader->binning_binary);
+ ir3_shader_destroy(shader->ir3_shader);
vk_free2(&dev->alloc, alloc, shader);
}
-void
-tu_shader_compile_options_init(
- struct tu_shader_compile_options *options,
- const VkGraphicsPipelineCreateInfo *pipeline_info)
-{
- bool has_gs = false;
- bool msaa = false;
- if (pipeline_info) {
- for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
- if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
- has_gs = true;
- break;
- }
- }
-
- const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
- const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
- vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
- if (!pipeline_info->pRasterizationState->rasterizerDiscardEnable &&
- (msaa_info->rasterizationSamples > 1 ||
- /* also set msaa key when sample location is not the default
- * since this affects varying interpolation */
- (sample_locations && sample_locations->sampleLocationsEnable))) {
- msaa = true;
- }
- }
-
- *options = (struct tu_shader_compile_options) {
- /* TODO: Populate the remaining fields of ir3_shader_key. */
- .key = {
- .has_gs = has_gs,
- .msaa = msaa,
- },
- /* TODO: VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
- * some optimizations need to happen otherwise shader might not compile
- */
- .optimize = true,
- .include_binning_pass = true,
- };
-}
-
-static uint32_t *
-tu_compile_shader_variant(struct ir3_shader *shader,
- const struct ir3_shader_key *key,
- struct ir3_shader_variant *nonbinning,
- struct ir3_shader_variant *variant)
-{
- variant->shader = shader;
- variant->type = shader->type;
- variant->key = *key;
- variant->binning_pass = !!nonbinning;
- variant->nonbinning = nonbinning;
-
- int ret = ir3_compile_shader_nir(shader->compiler, variant);
- if (ret)
- return NULL;
-
- /* when assemble fails, we rely on tu_shader_destroy to clean up the
- * variant
- */
- return ir3_shader_assemble(variant, shader->compiler->gpu_id);
-}
-
-VkResult
-tu_shader_compile(struct tu_device *dev,
- struct tu_shader *shader,
- const struct tu_shader *next_stage,
- const struct tu_shader_compile_options *options,
- const VkAllocationCallbacks *alloc)
-{
- if (options->optimize) {
- /* ignore the key for the first pass of optimization */
- ir3_optimize_nir(&shader->ir3_shader, shader->ir3_shader.nir, NULL);
-
- if (unlikely(dev->physical_device->instance->debug_flags &
- TU_DEBUG_NIR)) {
- fprintf(stderr, "optimized nir:\n");
- nir_print_shader(shader->ir3_shader.nir, stderr);
- }
- }
-
- shader->binary = tu_compile_shader_variant(
- &shader->ir3_shader, &options->key, NULL, &shader->variants[0]);
- if (!shader->binary)
- return VK_ERROR_OUT_OF_HOST_MEMORY;
-
- if (shader_debug_enabled(shader->ir3_shader.type)) {
- fprintf(stdout, "Native code for unnamed %s shader %s:\n",
- ir3_shader_stage(&shader->variants[0]), shader->ir3_shader.nir->info.name);
- if (shader->ir3_shader.type == MESA_SHADER_FRAGMENT)
- fprintf(stdout, "SIMD0\n");
- ir3_shader_disasm(&shader->variants[0], shader->binary, stdout);
- }
-
- /* compile another variant for the binning pass */
- if (options->include_binning_pass &&
- shader->ir3_shader.type == MESA_SHADER_VERTEX) {
- shader->binning_binary = tu_compile_shader_variant(
- &shader->ir3_shader, &options->key, &shader->variants[0],
- &shader->variants[1]);
- if (!shader->binning_binary)
- return VK_ERROR_OUT_OF_HOST_MEMORY;
-
- shader->has_binning_pass = true;
-
- if (shader_debug_enabled(MESA_SHADER_VERTEX)) {
- fprintf(stdout, "Native code for unnamed binning shader %s:\n",
- shader->ir3_shader.nir->info.name);
- ir3_shader_disasm(&shader->variants[1], shader->binary, stdout);
- }
- }
-
- if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_IR3)) {
- fprintf(stderr, "disassembled ir3:\n");
- fprintf(stderr, "shader: %s\n",
- gl_shader_stage_name(shader->ir3_shader.type));
- ir3_shader_disasm(&shader->variants[0], shader->binary, stderr);
-
- if (shader->has_binning_pass) {
- fprintf(stderr, "disassembled ir3:\n");
- fprintf(stderr, "shader: %s (binning)\n",
- gl_shader_stage_name(shader->ir3_shader.type));
- ir3_shader_disasm(&shader->variants[1], shader->binning_binary,
- stderr);
- }
- }
-
- return VK_SUCCESS;
-}
-
VkResult
tu_CreateShaderModule(VkDevice _device,
const VkShaderModuleCreateInfo *pCreateInfo,