gallivm: Use standard LLVMSetAlignment from LLVM 3.4 onwards.

[mesa.git] / src / gallium / auxiliary / gallivm / lp_bld_misc.cpp

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index e70a75fc6637d2037948fcd8f6a0117ac05af76c..61a50fa3b2e95f6dde8f36ca6e80fed24c837773 100644 (file)
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -61,6 +61,11 @@
 #include <llvm/Target/TargetOptions.h>
 #include <llvm/ExecutionEngine/ExecutionEngine.h>
 #include <llvm/ADT/Triple.h>
+#if HAVE_LLVM >= 0x0307
+#include <llvm/Analysis/TargetLibraryInfo.h>
+#else
+#include <llvm/Target/TargetLibraryInfo.h>
+#endif
 #if HAVE_LLVM < 0x0306
 #include <llvm/ExecutionEngine/JITMemoryManager.h>
 #else
@@ -147,6 +152,31 @@ lp_set_target_options(void)
    gallivm_init_llvm_targets();
 }
 
+extern "C"
+LLVMTargetLibraryInfoRef
+gallivm_create_target_library_info(const char *triple)
+{
+   return reinterpret_cast<LLVMTargetLibraryInfoRef>(
+#if HAVE_LLVM < 0x0307
+   new llvm::TargetLibraryInfo(
+#else
+   new llvm::TargetLibraryInfoImpl(
+#endif
+   llvm::Triple(triple)));
+}
+
+extern "C"
+void
+gallivm_dispose_target_library_info(LLVMTargetLibraryInfoRef library_info)
+{
+   delete reinterpret_cast<
+#if HAVE_LLVM < 0x0307
+   llvm::TargetLibraryInfo
+#else
+   llvm::TargetLibraryInfoImpl
+#endif
+   *>(library_info);
+}
 
 extern "C"
 LLVMValueRef
@@ -157,22 +187,28 @@ lp_build_load_volatile(LLVMBuilderRef B, LLVMValueRef PointerVal,
 }
 
 
-extern "C"
-void
-lp_set_load_alignment(LLVMValueRef Inst,
-                       unsigned Align)
-{
-   llvm::unwrap<llvm::LoadInst>(Inst)->setAlignment(Align);
-}
+#if HAVE_LLVM < 0x0304
 
 extern "C"
 void
-lp_set_store_alignment(LLVMValueRef Inst,
-                       unsigned Align)
+LLVMSetAlignmentBackport(LLVMValueRef V,
+                         unsigned Bytes)
 {
-   llvm::unwrap<llvm::StoreInst>(Inst)->setAlignment(Align);
+   switch (LLVMGetInstructionOpcode(V)) {
+   case LLVMLoad:
+      llvm::unwrap<llvm::LoadInst>(V)->setAlignment(Bytes);
+      break;
+   case LLVMStore:
+      llvm::unwrap<llvm::StoreInst>(V)->setAlignment(Bytes);
+      break;
+   default:
+      assert(0);
+      break;
+   }
 }
 
+#endif
+
 
 #if HAVE_LLVM < 0x0306
 typedef llvm::JITMemoryManager BaseMemoryManager;
@@ -498,50 +534,55 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT,
    }
 
    llvm::SmallVector<std::string, 16> MAttrs;
-   if (util_cpu_caps.has_sse) {
-      MAttrs.push_back("+sse");
-   }
-   if (util_cpu_caps.has_sse2) {
-      MAttrs.push_back("+sse2");
-   }
-   if (util_cpu_caps.has_sse3) {
-      MAttrs.push_back("+sse3");
-   }
-   if (util_cpu_caps.has_ssse3) {
-      MAttrs.push_back("+ssse3");
-   }
-   if (util_cpu_caps.has_sse4_1) {
+
+#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
+   /*
+    * We need to unset attributes because sometimes LLVM mistakenly assumes
+    * certain features are present given the processor name.
+    *
+    * https://bugs.freedesktop.org/show_bug.cgi?id=92214
+    * http://llvm.org/PR25021
+    * http://llvm.org/PR19429
+    * http://llvm.org/PR16721
+    */
+   MAttrs.push_back(util_cpu_caps.has_sse    ? "+sse"    : "-sse"   );
+   MAttrs.push_back(util_cpu_caps.has_sse2   ? "+sse2"   : "-sse2"  );
+   MAttrs.push_back(util_cpu_caps.has_sse3   ? "+sse3"   : "-sse3"  );
+   MAttrs.push_back(util_cpu_caps.has_ssse3  ? "+ssse3"  : "-ssse3" );
 #if HAVE_LLVM >= 0x0304
-      MAttrs.push_back("+sse4.1");
+   MAttrs.push_back(util_cpu_caps.has_sse4_1 ? "+sse4.1" : "-sse4.1");
 #else
-      MAttrs.push_back("+sse41");
+   MAttrs.push_back(util_cpu_caps.has_sse4_1 ? "+sse41"  : "-sse41" );
 #endif
-   }
-   if (util_cpu_caps.has_sse4_2) {
 #if HAVE_LLVM >= 0x0304
-      MAttrs.push_back("+sse4.2");
+   MAttrs.push_back(util_cpu_caps.has_sse4_2 ? "+sse4.2" : "-sse4.2");
 #else
-      MAttrs.push_back("+sse42");
+   MAttrs.push_back(util_cpu_caps.has_sse4_2 ? "+sse42"  : "-sse42" );
 #endif
-   }
-   if (util_cpu_caps.has_avx) {
-      /*
-       * AVX feature is not automatically detected from CPUID by the X86 target
-       * yet, because the old (yet default) JIT engine is not capable of
-       * emitting the opcodes. On newer llvm versions it is and at least some
-       * versions (tested with 3.3) will emit avx opcodes without this anyway.
-       */
-      MAttrs.push_back("+avx");
-      if (util_cpu_caps.has_f16c) {
-         MAttrs.push_back("+f16c");
-      }
-      if (util_cpu_caps.has_avx2) {
-         MAttrs.push_back("+avx2");
-      }
-   }
+   /*
+    * AVX feature is not automatically detected from CPUID by the X86 target
+    * yet, because the old (yet default) JIT engine is not capable of
+    * emitting the opcodes. On newer llvm versions it is and at least some
+    * versions (tested with 3.3) will emit avx opcodes without this anyway.
+    */
+   MAttrs.push_back(util_cpu_caps.has_avx  ? "+avx"  : "-avx");
+   MAttrs.push_back(util_cpu_caps.has_f16c ? "+f16c" : "-f16c");
+   MAttrs.push_back(util_cpu_caps.has_avx2 ? "+avx2" : "-avx2");
+#endif
+
+#if defined(PIPE_ARCH_PPC)
+   MAttrs.push_back(util_cpu_caps.has_altivec ? "+altivec" : "-altivec");
+#if HAVE_LLVM >= 0x0304
+   /*
+    * Make sure VSX instructions are disabled
+    * See LLVM bug https://llvm.org/bugs/show_bug.cgi?id=25503#c7
+    */
    if (util_cpu_caps.has_altivec) {
-      MAttrs.push_back("+altivec");
+      MAttrs.push_back("-vsx");
    }
+#endif
+#endif
+
    builder.setMAttrs(MAttrs);
 
 #if HAVE_LLVM >= 0x0305