panfrost/midgard: Use unsigned blend patch offset

[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_info.c

diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 36be463dc84d6cf7c8dcbfac7ee8b30b5af42bb0..37e16cca4281e0d058018327d8a63b2370bf65ac 100644 (file)
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -51,10 +51,14 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
 #undef OPCODE_GAP
 
 const struct tgsi_opcode_info *
-tgsi_get_opcode_info( uint opcode )
+tgsi_get_opcode_info(enum tgsi_opcode opcode)
 {
    static boolean firsttime = 1;
 
+   ASSERT_BITFIELD_SIZE(struct tgsi_opcode_info, opcode, TGSI_OPCODE_LAST - 1);
+   ASSERT_BITFIELD_SIZE(struct tgsi_opcode_info, output_mode,
+                        TGSI_OUTPUT_OTHER);
+
    if (firsttime) {
       unsigned i;
       firsttime = 0;
@@ -81,7 +85,7 @@ static const char * const opcode_names[TGSI_OPCODE_LAST] =
 #undef OPCODE_GAP
 
 const char *
-tgsi_get_opcode_name( uint opcode )
+tgsi_get_opcode_name(enum tgsi_opcode opcode)
 {
    if (opcode >= ARRAY_SIZE(opcode_names))
       return "UNK_OOB";
@@ -90,7 +94,7 @@ tgsi_get_opcode_name( uint opcode )
 
 
 const char *
-tgsi_get_processor_name( uint processor )
+tgsi_get_processor_name(enum pipe_shader_type processor)
 {
    switch (processor) {
    case PIPE_SHADER_VERTEX:
@@ -116,7 +120,7 @@ tgsi_get_processor_name( uint processor )
  * MOV and UCMP is special so return VOID
  */
 static inline enum tgsi_opcode_type
-tgsi_opcode_infer_type( uint opcode )
+tgsi_opcode_infer_type(enum tgsi_opcode opcode)
 {
    switch (opcode) {
    case TGSI_OPCODE_MOV:
@@ -146,9 +150,8 @@ tgsi_opcode_infer_type( uint opcode )
    case TGSI_OPCODE_UBFE:
    case TGSI_OPCODE_BFI:
    case TGSI_OPCODE_BREV:
-   case TGSI_OPCODE_POPC:
-   case TGSI_OPCODE_LSB:
-   case TGSI_OPCODE_UMSB:
+   case TGSI_OPCODE_IMG2HND:
+   case TGSI_OPCODE_SAMP2HND:
       return TGSI_TYPE_UNSIGNED;
    case TGSI_OPCODE_ARL:
    case TGSI_OPCODE_ARR:
@@ -182,6 +185,9 @@ tgsi_opcode_infer_type( uint opcode )
    case TGSI_OPCODE_U64SGE:
    case TGSI_OPCODE_I64SLT:
    case TGSI_OPCODE_I64SGE:
+   case TGSI_OPCODE_LSB:
+   case TGSI_OPCODE_POPC:
+   case TGSI_OPCODE_UMSB:
       return TGSI_TYPE_SIGNED;
    case TGSI_OPCODE_DADD:
    case TGSI_OPCODE_DABS:
@@ -242,11 +248,24 @@ tgsi_opcode_infer_type( uint opcode )
  * infer the source type of a TGSI opcode.
  */
 enum tgsi_opcode_type
-tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
+tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint src_idx)
 {
-   if (src_idx == 1 && opcode == TGSI_OPCODE_DLDEXP)
+   if (src_idx == 1 &&
+       (opcode == TGSI_OPCODE_DLDEXP || opcode == TGSI_OPCODE_LDEXP))
       return TGSI_TYPE_SIGNED;
 
+   if (src_idx == 1 &&
+       (opcode == TGSI_OPCODE_LOAD))
+      return TGSI_TYPE_UNSIGNED;
+
+   if (src_idx == 0 &&
+       (opcode == TGSI_OPCODE_STORE))
+      return TGSI_TYPE_UNSIGNED;
+
+   if (src_idx == 1 &&
+       opcode >= TGSI_OPCODE_ATOMUADD && opcode <= TGSI_OPCODE_ATOMIMAX)
+      return TGSI_TYPE_UNSIGNED;
+
    switch (opcode) {
    case TGSI_OPCODE_UIF:
    case TGSI_OPCODE_TXF:
@@ -262,6 +281,7 @@ tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
    case TGSI_OPCODE_UP2H:
    case TGSI_OPCODE_U2I64:
    case TGSI_OPCODE_MEMBAR:
+   case TGSI_OPCODE_UMSB:
       return TGSI_TYPE_UNSIGNED;
    case TGSI_OPCODE_IMUL_HI:
    case TGSI_OPCODE_I2F:
@@ -312,7 +332,10 @@ tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
  * infer the destination type of a TGSI opcode.
  */
 enum tgsi_opcode_type
-tgsi_opcode_infer_dst_type( uint opcode )
+tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode, uint dst_idx)
 {
+   if (dst_idx == 1 && opcode == TGSI_OPCODE_DFRACEXP)
+      return TGSI_TYPE_SIGNED;
+
    return tgsi_opcode_infer_type(opcode);
 }