/**************************************************************************
*
- * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2008 VMware, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "tgsi_info.h"
#include "tgsi_iterate.h"
+
+DEBUG_GET_ONCE_BOOL_OPTION(print_sanity, "TGSI_PRINT_SANITY", FALSE)
+
+
typedef struct {
uint file : 28;
/* max 2 dimensions */
uint errors;
uint warnings;
uint implied_array_size;
+ uint implied_out_array_size;
+
+ boolean print;
};
-static INLINE unsigned
+static inline unsigned
scan_register_key(const scan_register *reg)
{
unsigned key = reg->file;
scan_register_dst(scan_register *reg,
struct tgsi_full_dst_register *dst)
{
- fill_scan_register1d(reg,
- dst->Register.File,
- dst->Register.Index);
+ if (dst->Register.Dimension) {
+ /*FIXME: right now we don't support indirect
+ * multidimensional addressing */
+ fill_scan_register2d(reg,
+ dst->Register.File,
+ dst->Register.Index,
+ dst->Dimension.Index);
+ } else {
+ fill_scan_register1d(reg,
+ dst->Register.File,
+ dst->Register.Index);
+ }
}
static void
if (src->Register.Dimension) {
/*FIXME: right now we don't support indirect
* multidimensional addressing */
- debug_assert(!src->Dimension.Indirect);
fill_scan_register2d(reg,
src->Register.File,
src->Register.Index,
{
va_list args;
+ if (!ctx->print)
+ return;
+
debug_printf( "Error : " );
va_start( args, format );
_debug_vprintf( format, args );
{
va_list args;
+ if (!ctx->print)
+ return;
+
debug_printf( "Warning: " );
va_start( args, format );
_debug_vprintf( format, args );
struct cso_hash_iter iter =
cso_hash_first_node(ctx->regs_decl);
- while (cso_hash_iter_is_null(iter)) {
+ while (!cso_hash_iter_is_null(iter)) {
scan_register *reg = (scan_register *)cso_hash_iter_data(iter);
if (reg->file == file)
return TRUE;
"SAMP",
"ADDR",
"IMM",
- "LOOP",
- "PRED"
+ "SV",
+ "RES"
};
static boolean
boolean indirect_access )
{
if (!check_file_name( ctx, reg->file )) {
- free(reg);
+ FREE(reg);
return FALSE;
}
if (!is_ind_register_used(ctx, reg))
cso_hash_insert(ctx->regs_ind_used, reg->file, reg);
else
- free(reg);
+ FREE(reg);
}
else {
if (!is_register_declared( ctx, reg )) {
- if (reg->dimensions == 2)
+ if (reg->dimensions == 2) {
report_error( ctx, "%s[%d][%d]: Undeclared %s register", file_names[reg->file],
reg->indices[0], reg->indices[1], name );
- else
+ }
+ else {
report_error( ctx, "%s[%d]: Undeclared %s register", file_names[reg->file],
reg->indices[0], name );
}
+ }
if (!is_register_used( ctx, reg ))
cso_hash_insert(ctx->regs_used, scan_register_key(reg), reg);
else
- free(reg);
+ FREE(reg);
}
return TRUE;
}
uint i;
if (inst->Instruction.Opcode == TGSI_OPCODE_END) {
- if (ctx->index_of_END != ~0) {
+ if (ctx->index_of_END != ~0u) {
report_error( ctx, "Too many END instructions" );
}
ctx->index_of_END = ctx->num_instructions;
}
info = tgsi_get_opcode_info( inst->Instruction.Opcode );
- if (info == NULL) {
+ if (!info) {
report_error( ctx, "(%u): Invalid instruction opcode", inst->Instruction.Opcode );
return TRUE;
}
if (info->num_dst != inst->Instruction.NumDstRegs) {
- report_error( ctx, "%s: Invalid number of destination operands, should be %u", info->mnemonic, info->num_dst );
+ report_error( ctx, "%s: Invalid number of destination operands, should be %u",
+ tgsi_get_opcode_name(inst->Instruction.Opcode), info->num_dst );
}
if (info->num_src != inst->Instruction.NumSrcRegs) {
- report_error( ctx, "%s: Invalid number of source operands, should be %u", info->mnemonic, info->num_src );
+ report_error( ctx, "%s: Invalid number of source operands, should be %u",
+ tgsi_get_opcode_name(inst->Instruction.Opcode), info->num_src );
}
/* Check destination and source registers' validity.
reg,
"destination",
FALSE );
+ if (!inst->Dst[i].Register.WriteMask) {
+ report_error(ctx, "Destination register has empty writemask");
+ }
}
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
scan_register *reg = create_scan_register_src(&inst->Src[i]);
inst->Src[i].Indirect.Index);
check_register_usage(
ctx,
- reg,
+ ind_reg,
"indirect",
FALSE );
- if (!(reg->file == TGSI_FILE_ADDRESS || reg->file == TGSI_FILE_LOOP) ||
- reg->indices[0] != 0) {
- report_warning(ctx, "Indirect register neither ADDR[0] nor LOOP[0]");
- }
- }
- }
-
- switch (inst->Instruction.Opcode) {
- case TGSI_OPCODE_BGNFOR:
- case TGSI_OPCODE_ENDFOR:
- if (inst->Dst[0].Register.File != TGSI_FILE_LOOP ||
- inst->Dst[0].Register.Index != 0) {
- report_error(ctx, "Destination register must be LOOP[0]");
}
- break;
- }
-
- switch (inst->Instruction.Opcode) {
- case TGSI_OPCODE_BGNFOR:
- if (inst->Src[0].Register.File != TGSI_FILE_CONSTANT &&
- inst->Src[0].Register.File != TGSI_FILE_IMMEDIATE) {
- report_error(ctx, "Source register file must be either CONST or IMM");
- }
- break;
}
ctx->num_instructions++;
if (!check_file_name( ctx, file ))
return TRUE;
for (i = decl->Range.First; i <= decl->Range.Last; i++) {
- /* declared TGSI_FILE_INPUT's for geometry processor
+ /* declared TGSI_FILE_INPUT's for geometry and tessellation
* have an implied second dimension */
- if (file == TGSI_FILE_INPUT &&
- ctx->iter.processor.Processor == TGSI_PROCESSOR_GEOMETRY) {
+ uint processor = ctx->iter.processor.Processor;
+ uint patch = decl->Semantic.Name == TGSI_SEMANTIC_PATCH ||
+ decl->Semantic.Name == TGSI_SEMANTIC_TESSOUTER ||
+ decl->Semantic.Name == TGSI_SEMANTIC_TESSINNER;
+ if (file == TGSI_FILE_INPUT && !patch && (
+ processor == PIPE_SHADER_GEOMETRY ||
+ processor == PIPE_SHADER_TESS_CTRL ||
+ processor == PIPE_SHADER_TESS_EVAL)) {
uint vert;
for (vert = 0; vert < ctx->implied_array_size; ++vert) {
scan_register *reg = MALLOC(sizeof(scan_register));
- fill_scan_register2d(reg, file, vert, i);
+ fill_scan_register2d(reg, file, i, vert);
+ check_and_declare(ctx, reg);
+ }
+ } else if (file == TGSI_FILE_OUTPUT && !patch &&
+ processor == PIPE_SHADER_TESS_CTRL) {
+ uint vert;
+ for (vert = 0; vert < ctx->implied_out_array_size; ++vert) {
+ scan_register *reg = MALLOC(sizeof(scan_register));
+ fill_scan_register2d(reg, file, i, vert);
check_and_declare(ctx, reg);
}
} else {
scan_register *reg = MALLOC(sizeof(scan_register));
- fill_scan_register1d(reg, file, i);
+ if (decl->Declaration.Dimension) {
+ fill_scan_register2d(reg, file, i, decl->Dim.Index2D);
+ } else {
+ fill_scan_register1d(reg, file, i);
+ }
check_and_declare(ctx, reg);
}
}
/* Check data type validity.
*/
- if (imm->Immediate.DataType != TGSI_IMM_FLOAT32) {
+ if (imm->Immediate.DataType != TGSI_IMM_FLOAT32 &&
+ imm->Immediate.DataType != TGSI_IMM_UINT32 &&
+ imm->Immediate.DataType != TGSI_IMM_INT32) {
report_error( ctx, "(%u): Invalid immediate data type", imm->Immediate.DataType );
return TRUE;
}
{
struct sanity_check_ctx *ctx = (struct sanity_check_ctx *) iter;
- if (iter->processor.Processor == TGSI_PROCESSOR_GEOMETRY &&
+ if (iter->processor.Processor == PIPE_SHADER_GEOMETRY &&
prop->Property.PropertyName == TGSI_PROPERTY_GS_INPUT_PRIM) {
ctx->implied_array_size = u_vertices_per_prim(prop->u[0].Data);
}
+ if (iter->processor.Processor == PIPE_SHADER_TESS_CTRL &&
+ prop->Property.PropertyName == TGSI_PROPERTY_TCS_VERTICES_OUT)
+ ctx->implied_out_array_size = prop->u[0].Data;
+ return TRUE;
+}
+
+static boolean
+prolog(struct tgsi_iterate_context *iter)
+{
+ struct sanity_check_ctx *ctx = (struct sanity_check_ctx *) iter;
+ if (iter->processor.Processor == PIPE_SHADER_TESS_CTRL ||
+ iter->processor.Processor == PIPE_SHADER_TESS_EVAL)
+ ctx->implied_array_size = 32;
return TRUE;
}
/* There must be an END instruction somewhere.
*/
- if (ctx->index_of_END == ~0) {
+ if (ctx->index_of_END == ~0u) {
report_error( ctx, "Missing END instruction" );
}
struct cso_hash_iter iter =
cso_hash_first_node(ctx->regs_decl);
- while (cso_hash_iter_is_null(iter)) {
+ while (!cso_hash_iter_is_null(iter)) {
scan_register *reg = (scan_register *)cso_hash_iter_data(iter);
if (!is_register_used(ctx, reg) && !is_ind_register_used(ctx, reg)) {
report_warning( ctx, "%s[%u]: Register never used",
while (!cso_hash_iter_is_null(iter)) {
scan_register *reg = (scan_register *)cso_hash_iter_data(iter);
iter = cso_hash_erase(hash, iter);
- free(reg);
+ assert(reg->file < TGSI_FILE_COUNT);
+ FREE(reg);
}
cso_hash_delete(hash);
}
const struct tgsi_token *tokens )
{
struct sanity_check_ctx ctx;
+ boolean retval;
- ctx.iter.prolog = NULL;
+ ctx.iter.prolog = prolog;
ctx.iter.iterate_instruction = iter_instruction;
ctx.iter.iterate_declaration = iter_declaration;
ctx.iter.iterate_immediate = iter_immediate;
ctx.errors = 0;
ctx.warnings = 0;
ctx.implied_array_size = 0;
+ ctx.print = debug_get_option_print_sanity();
- if (!tgsi_iterate_shader( tokens, &ctx.iter ))
- return FALSE;
-
+ retval = tgsi_iterate_shader( tokens, &ctx.iter );
regs_hash_destroy(ctx.regs_decl);
regs_hash_destroy(ctx.regs_used);
regs_hash_destroy(ctx.regs_ind_used);
+ if (retval == FALSE)
+ return FALSE;
+
return ctx.errors == 0;
}
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