return file == TGSI_FILE_SAMPLER ||
file == TGSI_FILE_SAMPLER_VIEW ||
file == TGSI_FILE_IMAGE ||
- file == TGSI_FILE_BUFFER;
+ file == TGSI_FILE_BUFFER ||
+ file == TGSI_FILE_HW_ATOMIC;
}
static bool
-is_mem_query_inst(unsigned opcode)
+is_mem_query_inst(enum tgsi_opcode opcode)
{
return opcode == TGSI_OPCODE_RESQ ||
opcode == TGSI_OPCODE_TXQ ||
opcode == TGSI_OPCODE_TXQS ||
- opcode == TGSI_OPCODE_TXQ_LZ ||
opcode == TGSI_OPCODE_LODQ;
}
* texture map?
*/
static bool
-is_texture_inst(unsigned opcode)
+is_texture_inst(enum tgsi_opcode opcode)
{
return (!is_mem_query_inst(opcode) &&
tgsi_get_opcode_info(opcode)->is_tex);
* implicitly?
*/
static bool
-computes_derivative(unsigned opcode)
+computes_derivative(enum tgsi_opcode opcode)
{
if (tgsi_get_opcode_info(opcode)->is_tex) {
return opcode != TGSI_OPCODE_TG4 &&
opcode != TGSI_OPCODE_TXL &&
opcode != TGSI_OPCODE_TXL2 &&
opcode != TGSI_OPCODE_TXQ &&
- opcode != TGSI_OPCODE_TXQ_LZ &&
opcode != TGSI_OPCODE_TXQS;
}
const struct tgsi_full_instruction *fullinst,
const struct tgsi_full_src_register *src,
unsigned src_index,
- unsigned usage_mask,
+ unsigned usage_mask_after_swizzle,
bool is_interp_instruction,
bool *is_mem_inst)
{
if (info->processor == PIPE_SHADER_COMPUTE &&
src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
- unsigned swizzle[4], i, name;
+ unsigned name, mask;
name = info->system_value_semantic_name[src->Register.Index];
- swizzle[0] = src->Register.SwizzleX;
- swizzle[1] = src->Register.SwizzleY;
- swizzle[2] = src->Register.SwizzleZ;
- swizzle[3] = src->Register.SwizzleW;
switch (name) {
case TGSI_SEMANTIC_THREAD_ID:
case TGSI_SEMANTIC_BLOCK_ID:
- for (i = 0; i < 4; i++) {
- if (swizzle[i] <= TGSI_SWIZZLE_Z) {
- if (name == TGSI_SEMANTIC_THREAD_ID)
- info->uses_thread_id[swizzle[i]] = true;
- else
- info->uses_block_id[swizzle[i]] = true;
- }
+ mask = usage_mask_after_swizzle & TGSI_WRITEMASK_XYZ;
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+
+ if (name == TGSI_SEMANTIC_THREAD_ID)
+ info->uses_thread_id[i] = true;
+ else
+ info->uses_block_id[i] = true;
}
break;
case TGSI_SEMANTIC_BLOCK_SIZE:
if (src->Register.File == TGSI_FILE_INPUT) {
if (src->Register.Indirect) {
for (ind = 0; ind < info->num_inputs; ++ind) {
- info->input_usage_mask[ind] |= usage_mask;
+ info->input_usage_mask[ind] |= usage_mask_after_swizzle;
}
} else {
assert(ind >= 0);
assert(ind < PIPE_MAX_SHADER_INPUTS);
- info->input_usage_mask[ind] |= usage_mask;
+ info->input_usage_mask[ind] |= usage_mask_after_swizzle;
}
if (info->processor == PIPE_SHADER_FRAGMENT) {
index = info->input_semantic_index[input];
if (name == TGSI_SEMANTIC_POSITION &&
- (src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
- src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
- src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
- src->Register.SwizzleW == TGSI_SWIZZLE_Z))
- info->reads_z = TRUE;
-
- if (name == TGSI_SEMANTIC_COLOR) {
- unsigned mask =
- (1 << src->Register.SwizzleX) |
- (1 << src->Register.SwizzleY) |
- (1 << src->Register.SwizzleZ) |
- (1 << src->Register.SwizzleW);
-
- info->colors_read |= mask << (index * 4);
- }
+ usage_mask_after_swizzle & TGSI_WRITEMASK_Z)
+ info->reads_z = true;
+
+ if (name == TGSI_SEMANTIC_COLOR)
+ info->colors_read |= usage_mask_after_swizzle << (index * 4);
/* Process only interpolated varyings. Don't include POSITION.
* Don't include integer varyings, because they are not
const unsigned index = src->Register.Index;
assert(fullinst->Instruction.Texture);
- assert(index < ARRAY_SIZE(info->is_msaa_sampler));
assert(index < PIPE_MAX_SAMPLERS);
if (is_texture_inst(fullinst->Instruction.Opcode)) {
*/
assert(info->sampler_targets[index] == target);
}
- /* MSAA samplers */
- if (target == TGSI_TEXTURE_2D_MSAA ||
- target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
- info->is_msaa_sampler[src->Register.Index] = TRUE;
- }
}
}
unsigned i;
bool is_mem_inst = false;
bool is_interp_instruction = false;
+ unsigned sampler_src;
assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
info->opcode_count[fullinst->Instruction.Opcode]++;
case TGSI_OPCODE_ENDLOOP:
(*current_depth)--;
break;
+ case TGSI_OPCODE_TEX:
+ case TGSI_OPCODE_TEX_LZ:
+ case TGSI_OPCODE_TXB:
+ case TGSI_OPCODE_TXD:
+ case TGSI_OPCODE_TXL:
+ case TGSI_OPCODE_TXP:
+ case TGSI_OPCODE_TXQ:
+ case TGSI_OPCODE_TXQS:
+ case TGSI_OPCODE_TXF:
+ case TGSI_OPCODE_TXF_LZ:
+ case TGSI_OPCODE_TEX2:
+ case TGSI_OPCODE_TXB2:
+ case TGSI_OPCODE_TXL2:
+ case TGSI_OPCODE_TG4:
+ case TGSI_OPCODE_LODQ:
+ sampler_src = fullinst->Instruction.NumSrcRegs - 1;
+ if (fullinst->Src[sampler_src].Register.File != TGSI_FILE_SAMPLER)
+ info->uses_bindless_samplers = true;
+ break;
+ case TGSI_OPCODE_RESQ:
+ if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File))
+ info->uses_bindless_images = true;
+ break;
+ case TGSI_OPCODE_LOAD:
+ if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
+ info->uses_bindless_images = true;
+
+ if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
+ info->uses_bindless_buffer_load = true;
+ else
+ info->uses_bindless_image_load = true;
+ }
+ break;
+ case TGSI_OPCODE_ATOMUADD:
+ case TGSI_OPCODE_ATOMXCHG:
+ case TGSI_OPCODE_ATOMCAS:
+ case TGSI_OPCODE_ATOMAND:
+ case TGSI_OPCODE_ATOMOR:
+ case TGSI_OPCODE_ATOMXOR:
+ case TGSI_OPCODE_ATOMUMIN:
+ case TGSI_OPCODE_ATOMUMAX:
+ case TGSI_OPCODE_ATOMIMIN:
+ case TGSI_OPCODE_ATOMIMAX:
+ case TGSI_OPCODE_ATOMFADD:
+ if (tgsi_is_bindless_image_file(fullinst->Src[0].Register.File)) {
+ info->uses_bindless_images = true;
+
+ if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
+ info->uses_bindless_buffer_atomic = true;
+ else
+ info->uses_bindless_image_atomic = true;
+ }
+ break;
+ case TGSI_OPCODE_STORE:
+ if (tgsi_is_bindless_image_file(fullinst->Dst[0].Register.File)) {
+ info->uses_bindless_images = true;
+
+ if (fullinst->Memory.Texture == TGSI_TEXTURE_BUFFER)
+ info->uses_bindless_buffer_store = true;
+ else
+ info->uses_bindless_image_store = true;
+ }
+ break;
default:
break;
}
}
}
- if (fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
- fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG)
+ if ((fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
+ fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG) ||
+ fullinst->Instruction.Opcode == TGSI_OPCODE_DFMA ||
+ fullinst->Instruction.Opcode == TGSI_OPCODE_DDIV ||
+ fullinst->Instruction.Opcode == TGSI_OPCODE_D2U64 ||
+ fullinst->Instruction.Opcode == TGSI_OPCODE_D2I64 ||
+ fullinst->Instruction.Opcode == TGSI_OPCODE_U642D ||
+ fullinst->Instruction.Opcode == TGSI_OPCODE_I642D)
info->uses_doubles = TRUE;
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
scan_src_operand(info, fullinst, &fullinst->Src[i], i,
tgsi_util_get_inst_usage_mask(fullinst, i),
is_interp_instruction, &is_mem_inst);
+
+ if (fullinst->Src[i].Register.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = fullinst->Src[i].Indirect.File;
+ src.Register.Index = fullinst->Src[i].Indirect.Index;
+
+ scan_src_operand(info, fullinst, &src, -1,
+ 1 << fullinst->Src[i].Indirect.Swizzle,
+ false, NULL);
+ }
+
+ if (fullinst->Src[i].Register.Dimension &&
+ fullinst->Src[i].Dimension.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = fullinst->Src[i].DimIndirect.File;
+ src.Register.Index = fullinst->Src[i].DimIndirect.Index;
+
+ scan_src_operand(info, fullinst, &src, -1,
+ 1 << fullinst->Src[i].DimIndirect.Swizzle,
+ false, NULL);
+ }
}
if (fullinst->Instruction.Texture) {
src.Register.File = fullinst->TexOffsets[i].File;
src.Register.Index = fullinst->TexOffsets[i].Index;
- src.Register.SwizzleX = fullinst->TexOffsets[i].SwizzleX;
- src.Register.SwizzleY = fullinst->TexOffsets[i].SwizzleY;
- src.Register.SwizzleZ = fullinst->TexOffsets[i].SwizzleZ;
/* The usage mask is suboptimal but should be safe. */
- scan_src_operand(info, fullinst, &src, 0, TGSI_WRITEMASK_XYZ,
+ scan_src_operand(info, fullinst, &src, -1,
+ (1 << fullinst->TexOffsets[i].SwizzleX) |
+ (1 << fullinst->TexOffsets[i].SwizzleY) |
+ (1 << fullinst->TexOffsets[i].SwizzleZ),
false, &is_mem_inst);
}
}
/* check for indirect register writes */
for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
+
if (dst->Register.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = dst->Indirect.File;
+ src.Register.Index = dst->Indirect.Index;
+
+ scan_src_operand(info, fullinst, &src, -1,
+ 1 << dst->Indirect.Swizzle, false, NULL);
+
info->indirect_files |= (1 << dst->Register.File);
info->indirect_files_written |= (1 << dst->Register.File);
}
- if (dst->Register.Dimension && dst->Dimension.Indirect)
+ if (dst->Register.Dimension && dst->Dimension.Indirect) {
+ struct tgsi_full_src_register src = {{0}};
+
+ src.Register.File = dst->DimIndirect.File;
+ src.Register.Index = dst->DimIndirect.Index;
+
+ scan_src_operand(info, fullinst, &src, -1,
+ 1 << dst->DimIndirect.Swizzle, false, NULL);
+
info->dim_indirect_files |= 1u << dst->Register.File;
+ }
if (is_memory_file(dst->Register.File)) {
assert(fullinst->Instruction.Opcode == TGSI_OPCODE_STORE);
int buffer;
unsigned index, target, type;
- /* only first 32 regs will appear in this bitfield */
- info->file_mask[file] |= (1 << reg);
+ /*
+ * only first 32 regs will appear in this bitfield, if larger
+ * bits will wrap around.
+ */
+ info->file_mask[file] |= (1u << (reg & 31));
info->file_count[file]++;
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
/* Vertex shaders can have inputs with holes between them. */
info->num_inputs = MAX2(info->num_inputs, reg + 1);
- if (semName == TGSI_SEMANTIC_PRIMID)
- info->uses_primid = TRUE;
- else if (procType == PIPE_SHADER_FRAGMENT) {
- if (semName == TGSI_SEMANTIC_POSITION)
- info->reads_position = TRUE;
- else if (semName == TGSI_SEMANTIC_FACE)
- info->uses_frontface = TRUE;
+ switch (semName) {
+ case TGSI_SEMANTIC_PRIMID:
+ info->uses_primid = true;
+ break;
+ case TGSI_SEMANTIC_POSITION:
+ info->reads_position = true;
+ break;
+ case TGSI_SEMANTIC_FACE:
+ info->uses_frontface = true;
+ break;
}
break;
case TGSI_SEMANTIC_BASEVERTEX:
info->uses_basevertex = TRUE;
break;
+ case TGSI_SEMANTIC_DRAWID:
+ info->uses_drawid = TRUE;
+ break;
case TGSI_SEMANTIC_PRIMID:
info->uses_primid = TRUE;
break;
procType == PIPE_SHADER_TESS_EVAL ||
procType == PIPE_SHADER_COMPUTE);
info->processor = procType;
+ info->num_tokens = tgsi_num_tokens(parse.Tokens);
/**
** Loop over incoming program tokens/instructions
*/
while (!tgsi_parse_end_of_tokens(&parse)) {
- info->num_tokens++;
-
tgsi_parse_token( &parse );
switch( parse.FullToken.Token.Type ) {
return;
}
+
+static void
+check_no_subroutines(const struct tgsi_full_instruction *inst)
+{
+ switch (inst->Instruction.Opcode) {
+ case TGSI_OPCODE_BGNSUB:
+ case TGSI_OPCODE_ENDSUB:
+ case TGSI_OPCODE_CAL:
+ unreachable("subroutines unhandled");
+ }
+}
+
+static unsigned
+get_inst_tessfactor_writemask(const struct tgsi_shader_info *info,
+ const struct tgsi_full_instruction *inst)
+{
+ unsigned writemask = 0;
+
+ for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
+ const struct tgsi_full_dst_register *dst = &inst->Dst[i];
+
+ if (dst->Register.File == TGSI_FILE_OUTPUT &&
+ !dst->Register.Indirect) {
+ unsigned name = info->output_semantic_name[dst->Register.Index];
+
+ if (name == TGSI_SEMANTIC_TESSINNER)
+ writemask |= dst->Register.WriteMask;
+ else if (name == TGSI_SEMANTIC_TESSOUTER)
+ writemask |= dst->Register.WriteMask << 4;
+ }
+ }
+ return writemask;
+}
+
+static unsigned
+get_block_tessfactor_writemask(const struct tgsi_shader_info *info,
+ struct tgsi_parse_context *parse,
+ unsigned end_opcode)
+{
+ struct tgsi_full_instruction *inst;
+ unsigned writemask = 0;
+
+ tgsi_parse_token(parse);
+ assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
+ inst = &parse->FullToken.FullInstruction;
+ check_no_subroutines(inst);
+
+ while (inst->Instruction.Opcode != end_opcode) {
+
+ /* Recursively process nested blocks. */
+ switch (inst->Instruction.Opcode) {
+ case TGSI_OPCODE_IF:
+ case TGSI_OPCODE_UIF:
+ writemask |=
+ get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDIF);
+ break;
+
+ case TGSI_OPCODE_BGNLOOP:
+ writemask |=
+ get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
+ break;
+
+ case TGSI_OPCODE_BARRIER:
+ unreachable("nested BARRIER is illegal");
+ break;
+
+ default:
+ writemask |= get_inst_tessfactor_writemask(info, inst);
+ }
+
+ tgsi_parse_token(parse);
+ assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
+ inst = &parse->FullToken.FullInstruction;
+ check_no_subroutines(inst);
+ }
+
+ return writemask;
+}
+
+static void
+get_if_block_tessfactor_writemask(const struct tgsi_shader_info *info,
+ struct tgsi_parse_context *parse,
+ unsigned *upper_block_tf_writemask,
+ unsigned *cond_block_tf_writemask)
+{
+ struct tgsi_full_instruction *inst;
+ unsigned then_tessfactor_writemask = 0;
+ unsigned else_tessfactor_writemask = 0;
+ unsigned writemask;
+ bool is_then = true;
+
+ tgsi_parse_token(parse);
+ assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
+ inst = &parse->FullToken.FullInstruction;
+ check_no_subroutines(inst);
+
+ while (inst->Instruction.Opcode != TGSI_OPCODE_ENDIF) {
+
+ switch (inst->Instruction.Opcode) {
+ case TGSI_OPCODE_ELSE:
+ is_then = false;
+ break;
+
+ /* Recursively process nested blocks. */
+ case TGSI_OPCODE_IF:
+ case TGSI_OPCODE_UIF:
+ get_if_block_tessfactor_writemask(info, parse,
+ is_then ? &then_tessfactor_writemask :
+ &else_tessfactor_writemask,
+ cond_block_tf_writemask);
+ break;
+
+ case TGSI_OPCODE_BGNLOOP:
+ *cond_block_tf_writemask |=
+ get_block_tessfactor_writemask(info, parse, TGSI_OPCODE_ENDLOOP);
+ break;
+
+ case TGSI_OPCODE_BARRIER:
+ unreachable("nested BARRIER is illegal");
+ break;
+ default:
+ /* Process an instruction in the current block. */
+ writemask = get_inst_tessfactor_writemask(info, inst);
+
+ if (writemask) {
+ if (is_then)
+ then_tessfactor_writemask |= writemask;
+ else
+ else_tessfactor_writemask |= writemask;
+ }
+ }
+
+ tgsi_parse_token(parse);
+ assert(parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION);
+ inst = &parse->FullToken.FullInstruction;
+ check_no_subroutines(inst);
+ }
+
+ if (then_tessfactor_writemask || else_tessfactor_writemask) {
+ /* If both statements write the same tess factor channels,
+ * we can say that the upper block writes them too. */
+ *upper_block_tf_writemask |= then_tessfactor_writemask &
+ else_tessfactor_writemask;
+ *cond_block_tf_writemask |= then_tessfactor_writemask |
+ else_tessfactor_writemask;
+ }
+}
+
+void
+tgsi_scan_tess_ctrl(const struct tgsi_token *tokens,
+ const struct tgsi_shader_info *info,
+ struct tgsi_tessctrl_info *out)
+{
+ memset(out, 0, sizeof(*out));
+
+ if (info->processor != PIPE_SHADER_TESS_CTRL)
+ return;
+
+ struct tgsi_parse_context parse;
+ if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
+ debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
+ return;
+ }
+
+ /* The pass works as follows:
+ * If all codepaths write tess factors, we can say that all invocations
+ * define tess factors.
+ *
+ * Each tess factor channel is tracked separately.
+ */
+ unsigned main_block_tf_writemask = 0; /* if main block writes tess factors */
+ unsigned cond_block_tf_writemask = 0; /* if cond block writes tess factors */
+
+ /* Initial value = true. Here the pass will accumulate results from multiple
+ * segments surrounded by barriers. If tess factors aren't written at all,
+ * it's a shader bug and we don't care if this will be true.
+ */
+ out->tessfactors_are_def_in_all_invocs = true;
+
+ while (!tgsi_parse_end_of_tokens(&parse)) {
+ tgsi_parse_token(&parse);
+
+ if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
+ continue;
+
+ struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
+ check_no_subroutines(inst);
+
+ /* Process nested blocks. */
+ switch (inst->Instruction.Opcode) {
+ case TGSI_OPCODE_IF:
+ case TGSI_OPCODE_UIF:
+ get_if_block_tessfactor_writemask(info, &parse,
+ &main_block_tf_writemask,
+ &cond_block_tf_writemask);
+ continue;
+
+ case TGSI_OPCODE_BGNLOOP:
+ cond_block_tf_writemask |=
+ get_block_tessfactor_writemask(info, &parse, TGSI_OPCODE_ENDLOOP);
+ continue;
+
+ case TGSI_OPCODE_BARRIER:
+ /* The following case must be prevented:
+ * gl_TessLevelInner = ...;
+ * barrier();
+ * if (gl_InvocationID == 1)
+ * gl_TessLevelInner = ...;
+ *
+ * If you consider disjoint code segments separated by barriers, each
+ * such segment that writes tess factor channels should write the same
+ * channels in all codepaths within that segment.
+ */
+ if (main_block_tf_writemask || cond_block_tf_writemask) {
+ /* Accumulate the result: */
+ out->tessfactors_are_def_in_all_invocs &=
+ !(cond_block_tf_writemask & ~main_block_tf_writemask);
+
+ /* Analyze the next code segment from scratch. */
+ main_block_tf_writemask = 0;
+ cond_block_tf_writemask = 0;
+ }
+ continue;
+ }
+
+ main_block_tf_writemask |= get_inst_tessfactor_writemask(info, inst);
+ }
+
+ /* Accumulate the result for the last code segment separated by a barrier. */
+ if (main_block_tf_writemask || cond_block_tf_writemask) {
+ out->tessfactors_are_def_in_all_invocs &=
+ !(cond_block_tf_writemask & ~main_block_tf_writemask);
+ }
+
+ tgsi_parse_free(&parse);
+}
projects / mesa.git / blobdiff