38,46,54,62,39,47,55,63
};
+const int vl_zscan_h265_up_right_diagonal_16[] =
+{
+ /* Up-right diagonal scan order for 4x4 blocks - see H.265 section 6.5.3. */
+ 0, 4, 1, 8, 5, 2, 12, 9,
+ 6, 3, 13, 10, 7, 14, 11, 15,
+};
+
+const int vl_zscan_h265_up_right_diagonal[] =
+{
+ /* Up-right diagonal scan order for 8x8 blocks - see H.265 section 6.5.3. */
+ 0, 8, 1, 16, 9, 2, 24, 17,
+ 10, 3, 32, 25, 18, 11, 4, 40,
+ 33, 26, 19, 12, 5, 48, 41, 34,
+ 27, 20, 13, 6, 56, 49, 42, 35,
+ 28, 21, 14, 7, 57, 50, 43, 36,
+ 29, 22, 15, 58, 51, 44, 37, 30,
+ 23, 59, 52, 45, 38, 31, 60, 53,
+ 46, 39, 61, 54, 47, 62, 55, 63,
+};
+
+
static void *
create_vert_shader(struct vl_zscan *zscan)
{
struct ureg_program *shader;
-
struct ureg_src scale;
struct ureg_src vrect, vpos, block_num;
-
struct ureg_dst tmp;
struct ureg_dst o_vpos;
struct ureg_dst *o_vtex;
+ unsigned i;
- signed i;
-
- shader = ureg_create(TGSI_PROCESSOR_VERTEX);
+ shader = ureg_create(PIPE_SHADER_VERTEX);
if (!shader)
return NULL;
for (i = 0; i < zscan->num_channels; ++i) {
ureg_ADD(shader, ureg_writemask(tmp, TGSI_WRITEMASK_X), ureg_scalar(ureg_src(tmp), TGSI_SWIZZLE_Y),
ureg_imm1f(shader, 1.0f / (zscan->blocks_per_line * VL_BLOCK_WIDTH)
- * (i - (signed)zscan->num_channels / 2)));
+ * ((signed)i - (signed)zscan->num_channels / 2)));
ureg_MAD(shader, ureg_writemask(o_vtex[i], TGSI_WRITEMASK_X), vrect,
ureg_imm1f(shader, 1.0f / zscan->blocks_per_line), ureg_src(tmp));
unsigned i;
- shader = ureg_create(TGSI_PROCESSOR_FRAGMENT);
+ shader = ureg_create(PIPE_SHADER_FRAGMENT);
if (!shader)
return NULL;