gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.

[mesa.git] / src / gallium / docs / source / screen.rst

diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst
index 553b8e661a4fdd70569701ca995236dd406a3fa7..bc0db429b38435d11d062dbca3a6585f71e7c08d 100644 (file)
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -406,6 +406,11 @@ The integer capabilities:
 * ``PIPE_CAP_MEMOBJ``: Whether operations on memory objects are supported.
 * ``PIPE_CAP_LOAD_CONSTBUF``: True if the driver supports TGSI_OPCODE_LOAD use
   with constant buffers.
+* ``PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS``: Any TGSI register can be used as
+  an address for indirect register indexing.
+* ``PIPE_CAP_TILE_RASTER_ORDER``: Whether the driver supports
+  GL_MESA_tile_raster_order, using the tile_raster_order_* fields in
+  pipe_rasterizer_state.
 
 
 .. _pipe_capf: