texture arrays and 2D textures. address.w is always
ignored.
+.. opcode:: STORE - Write data to a shader resource
+
+ Syntax: ``STORE resource, address, src``
+
+ Example: ``STORE RES[0], TEMP[0], TEMP[1]``
+
+ Using the provided integer address, STORE writes data
+ to the specified buffer or texture.
+
+ The 'address' is specified as a vector of unsigned
+ integers. If the 'address' is out of range the result
+ is unspecified.
+
+ Only the first mipmap level of a resource can be
+ written to using this instruction.
+
+ For 1D or 2D texture arrays, the array index is
+ provided as an unsigned integer in address.y or
+ address.z, respectively. address.yz are ignored for
+ buffers and 1D textures. address.z is ignored for 1D
+ texture arrays and 2D textures. address.w is always
+ ignored.
+
+
+.. _threadsyncopcodes:
+
+Inter-thread synchronization opcodes
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+These opcodes are intended for communication between threads running
+within the same compute grid. For now they're only valid in compute
+programs.
+
+.. opcode:: MFENCE - Memory fence
+
+ Syntax: ``MFENCE resource``
+
+ Example: ``MFENCE RES[0]``
+
+ This opcode forces strong ordering between any memory access
+ operations that affect the specified resource. This means that
+ previous loads and stores (and only those) will be performed and
+ visible to other threads before the program execution continues.
+
+
+.. opcode:: LFENCE - Load memory fence
+
+ Syntax: ``LFENCE resource``
+
+ Example: ``LFENCE RES[0]``
+
+ Similar to MFENCE, but it only affects the ordering of memory loads.
+
+
+.. opcode:: SFENCE - Store memory fence
+
+ Syntax: ``SFENCE resource``
+
+ Example: ``SFENCE RES[0]``
+
+ Similar to MFENCE, but it only affects the ordering of memory stores.
+
+
+.. opcode:: BARRIER - Thread group barrier
+
+ ``BARRIER``
+
+ This opcode suspends the execution of the current thread until all
+ the remaining threads in the working group reach the same point of
+ the program. Results are unspecified if any of the remaining
+ threads terminates or never reaches an executed BARRIER instruction.
+
+
+.. _atomopcodes:
+
+Atomic opcodes
+^^^^^^^^^^^^^^
+
+These opcodes provide atomic variants of some common arithmetic and
+logical operations. In this context atomicity means that another
+concurrent memory access operation that affects the same memory
+location is guaranteed to be performed strictly before or after the
+entire execution of the atomic operation.
+
+For the moment they're only valid in compute programs.
+
+.. opcode:: ATOMUADD - Atomic integer addition
+
+ Syntax: ``ATOMUADD dst, resource, offset, src``
+
+ Example: ``ATOMUADD TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = dst_i + src_i
+
+
+.. opcode:: ATOMXCHG - Atomic exchange
+
+ Syntax: ``ATOMXCHG dst, resource, offset, src``
+
+ Example: ``ATOMXCHG TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = src_i
+
+
+.. opcode:: ATOMCAS - Atomic compare-and-exchange
+
+ Syntax: ``ATOMCAS dst, resource, offset, cmp, src``
+
+ Example: ``ATOMCAS TEMP[0], RES[0], TEMP[1], TEMP[2], TEMP[3]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = (dst_i == cmp_i ? src_i : dst_i)
+
+
+.. opcode:: ATOMAND - Atomic bitwise And
+
+ Syntax: ``ATOMAND dst, resource, offset, src``
+
+ Example: ``ATOMAND TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = dst_i \& src_i
+
+
+.. opcode:: ATOMOR - Atomic bitwise Or
+
+ Syntax: ``ATOMOR dst, resource, offset, src``
+
+ Example: ``ATOMOR TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = dst_i | src_i
+
+
+.. opcode:: ATOMXOR - Atomic bitwise Xor
+
+ Syntax: ``ATOMXOR dst, resource, offset, src``
+
+ Example: ``ATOMXOR TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = dst_i \oplus src_i
+
+
+.. opcode:: ATOMUMIN - Atomic unsigned minimum
+
+ Syntax: ``ATOMUMIN dst, resource, offset, src``
+
+ Example: ``ATOMUMIN TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = (dst_i < src_i ? dst_i : src_i)
+
+
+.. opcode:: ATOMUMAX - Atomic unsigned maximum
+
+ Syntax: ``ATOMUMAX dst, resource, offset, src``
+
+ Example: ``ATOMUMAX TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = (dst_i > src_i ? dst_i : src_i)
+
+
+.. opcode:: ATOMIMIN - Atomic signed minimum
+
+ Syntax: ``ATOMIMIN dst, resource, offset, src``
+
+ Example: ``ATOMIMIN TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = (dst_i < src_i ? dst_i : src_i)
+
+
+.. opcode:: ATOMIMAX - Atomic signed maximum
+
+ Syntax: ``ATOMIMAX dst, resource, offset, src``
+
+ Example: ``ATOMIMAX TEMP[0], RES[0], TEMP[1], TEMP[2]``
+
+ The following operation is performed atomically on each component:
+
+.. math::
+
+ dst_i = resource[offset]_i
+
+ resource[offset]_i = (dst_i > src_i ? dst_i : src_i)
+
+
Explanation of symbols used
------------------------------
UsageMask field specifies which of the register components can be accessed
and is one of TGSI_WRITEMASK.
+The Local flag specifies that a given value isn't intended for
+subroutine parameter passing and, as a result, the implementation
+isn't required to give any guarantees of it being preserved across
+subroutine boundaries. As it's merely a compiler hint, the
+implementation is free to ignore it.
+
If Dimension flag is set to 1, a Declaration Dimension token follows.
If Semantic flag is set to 1, a Declaration Semantic token follows.
Follows Declaration token if file is TGSI_FILE_RESOURCE.
- DCL RES[#], resource
+ DCL RES[#], resource [, WR] [, RAW]
Declares a shader input resource and assigns it to a RES[#]
register.
resource can be one of BUFFER, 1D, 2D, 3D, CUBE, 1DArray and
2DArray.
+ If the RAW keyword is not specified, the texture data will be
+ subject to conversion, swizzling and scaling as required to yield
+ the specified data type from the physical data format of the bound
+ resource.
+
+ If the RAW keyword is specified, no channel conversion will be
+ performed: the values read for each of the channels (X,Y,Z,W) will
+ correspond to consecutive words in the same order and format
+ they're found in memory. No element-to-address conversion will be
+ performed either: the value of the provided X coordinate will be
+ interpreted in byte units instead of texel units. The result of
+ accessing a misaligned address is undefined.
+
+ Usage of the STORE opcode is only allowed if the WR (writable) flag
+ is set.
+
Properties
^^^^^^^^^^^^^^^^^^^^^^^^
projects / mesa.git / blobdiff