{
struct pipe_texture base;
- unsigned long level_offset[PIPE_MAX_TEXTURE_LEVELS];
+ unsigned long level_offset[CELL_MAX_TEXTURE_LEVELS];
+ unsigned long stride[CELL_MAX_TEXTURE_LEVELS];
- /* The data is held here:
+ /**
+ * Display target, for textures with the PIPE_TEXTURE_USAGE_DISPLAY_TARGET
+ * usage.
+ */
+ struct sw_displaytarget *dt;
+
+ /**
+ * Malloc'ed data for regular textures, or a mapping to dt above.
+ */
+ void *data;
+
+ /* Size of the linear buffer??
*/
- struct pipe_buffer *buffer;
unsigned long buffer_size;
- void *tiled_data; /* XXX this may be temporary */ /*ALIGN16*/
+ /** The buffer above, mapped. This is the memory from which the
+ * SPUs will fetch texels. This texture data is in the tiled layout.
+ */
+ ubyte *mapped;
+};
+
+
+struct cell_transfer
+{
+ struct pipe_transfer base;
+
+ unsigned long offset;
+ void *map;
};
}
-
-extern void
-cell_update_texture_mapping(struct cell_context *cell);
+/** cast wrapper */
+static INLINE struct cell_transfer *
+cell_transfer(struct pipe_transfer *pt)
+{
+ return (struct cell_transfer *) pt;
+}
extern void
-cell_init_texture_functions(struct cell_context *cell);
+cell_init_screen_texture_funcs(struct pipe_screen *screen);
#endif /* CELL_TEXTURE_H */