unsigned use_blt : 1;
/* can use any kind of wrapping mode on npot textures */
unsigned npot_tex_any_wrap : 1;
+ /* supports seamless cube map */
+ unsigned seamless_cube_map : 1;
/* number of bits per TS tile */
unsigned bits_per_tile;
/* clear value for TS (dependent on bits_per_tile) */
uint32_t PE_STENCIL_CONFIG_EXT[2];
};
-/* Compiled pipe_scissor_state */
-struct compiled_scissor_state {
- uint32_t SE_SCISSOR_LEFT;
- uint32_t SE_SCISSOR_TOP;
- uint32_t SE_SCISSOR_RIGHT;
- uint32_t SE_SCISSOR_BOTTOM;
- uint32_t SE_CLIP_RIGHT;
- uint32_t SE_CLIP_BOTTOM;
-};
-
/* Compiled pipe_viewport_state */
struct compiled_viewport_state {
uint32_t PA_VIEWPORT_SCALE_X;
uint32_t SE_SCISSOR_TOP;
uint32_t SE_SCISSOR_RIGHT;
uint32_t SE_SCISSOR_BOTTOM;
- uint32_t SE_CLIP_RIGHT;
- uint32_t SE_CLIP_BOTTOM;
uint32_t PE_DEPTH_NEAR;
uint32_t PE_DEPTH_FAR;
};
struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
uint32_t PE_COLOR_STRIDE;
uint32_t PE_MEM_CONFIG;
- uint32_t SE_SCISSOR_LEFT;
- uint32_t SE_SCISSOR_TOP;
- uint32_t SE_SCISSOR_RIGHT;
- uint32_t SE_SCISSOR_BOTTOM;
- uint32_t SE_CLIP_RIGHT;
- uint32_t SE_CLIP_BOTTOM;
uint32_t RA_MULTISAMPLE_UNK00E04;
uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];