nir/lower_idiv: add new llvm-based path

[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_rs.c

diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c b/src/gallium/drivers/etnaviv/etnaviv_rs.c
index 2653fc21335fecb287b9b661938a36af4bbe951c..cba0f18a7a13ff740386fb826a9b42275fb0354f 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_rs.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_rs.c
@@ -105,23 +105,21 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
                         COND(rs->dest_tiling & 2, VIVS_RS_DEST_STRIDE_TILING) |
                         COND(dest_multi, VIVS_RS_DEST_STRIDE_MULTI);
 
-   if (ctx->specs.pixel_pipes == 1 || ctx->specs.single_buffer) {
-      cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
-                           VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height);
-   } else if (ctx->specs.pixel_pipes == 2) {
-      assert((rs->height & 7) == 0); /* GPU hangs happen if height not 8-aligned */
 
-      if (source_multi)
-         cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2;
+   if (source_multi)
+      cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2;
+
+   if (dest_multi)
+      cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2;
 
-      if (dest_multi)
-         cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2;
+   cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
+                        VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height);
 
+   /* use dual pipe mode when required */
+   if (!ctx->specs.single_buffer && ctx->specs.pixel_pipes == 2 && !(rs->height & 7)) {
       cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
-                           VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2);
+                              VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2);
       cs->RS_PIPE_OFFSET[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2);
-   } else {
-      abort();
    }
 
    cs->RS_DITHER[0] = rs->dither[0];
@@ -264,17 +262,15 @@ etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf,
    case 32:
       format = RS_FORMAT_A8R8G8B8;
       break;
+   case 64:
+      assert(ctx->specs.halti >= 2);
+      format = RS_FORMAT_64BPP_CLEAR;
+      break;
    default:
-      format = ETNA_NO_MATCH;
+      unreachable("bpp not supported for clear by RS");
       break;
    }
 
-   if (format == ETNA_NO_MATCH) {
-      BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s", util_format_name(surf->base.format));
-      format = RS_FORMAT_A8R8G8B8;
-      assert(0);
-   }
-
    /* use tiled clear if width is multiple of 16 */
    bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
                       (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
@@ -396,6 +392,7 @@ etna_clear_rs(struct pipe_context *pctx, unsigned buffers,
            const union pipe_color_union *color, double depth, unsigned stencil)
 {
    struct etna_context *ctx = etna_context(pctx);
+   mtx_lock(&ctx->lock);
 
    /* Flush color and depth cache before clearing anything.
     * This is especially important when coming from another surface, as
@@ -441,6 +438,7 @@ etna_clear_rs(struct pipe_context *pctx, unsigned buffers,
       etna_blit_clear_zs_rs(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil);
 
    etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
+   mtx_unlock(&ctx->lock);
 }
 
 static bool
@@ -526,14 +524,13 @@ etna_get_rs_alignment_mask(const struct etna_context *ctx,
    unsigned int h_align, w_align;
 
    if (layout & ETNA_LAYOUT_BIT_SUPER) {
-      w_align = h_align = 64;
+      w_align = 64;
+      h_align = 64 * ctx->specs.pixel_pipes;
    } else {
       w_align = ETNA_RS_WIDTH_MASK + 1;
       h_align = ETNA_RS_HEIGHT_MASK + 1;
    }
 
-   h_align *= ctx->screen->specs.pixel_pipes;
-
    *width_mask = w_align - 1;
    *height_mask = h_align -1;
 }
@@ -601,15 +598,6 @@ etna_try_rs_blit(struct pipe_context *pctx,
    if ((blit_info->dst.box.x & w_mask) || (blit_info->dst.box.y & h_mask))
       return false;
 
-   /* Ensure that the Z coordinate is sane */
-   if (dst->base.target != PIPE_TEXTURE_CUBE)
-      assert(blit_info->dst.box.z == 0);
-   if (src->base.target != PIPE_TEXTURE_CUBE)
-      assert(blit_info->src.box.z == 0);
-
-   assert(blit_info->src.box.z < src->base.array_size);
-   assert(blit_info->dst.box.z < dst->base.array_size);
-
    struct etna_resource_level *src_lev = &src->levels[blit_info->src.level];
    struct etna_resource_level *dst_lev = &dst->levels[blit_info->dst.level];
 
@@ -645,7 +633,7 @@ etna_try_rs_blit(struct pipe_context *pctx,
    unsigned int width = blit_info->src.box.width * msaa_xscale;
    unsigned int height = blit_info->src.box.height * msaa_yscale;
    unsigned int w_align = ETNA_RS_WIDTH_MASK + 1;
-   unsigned int h_align = (ETNA_RS_HEIGHT_MASK + 1) * ctx->specs.pixel_pipes;
+   unsigned int h_align = ETNA_RS_HEIGHT_MASK + 1;
 
    if (width & (w_align - 1) && width >= src_lev->width * msaa_xscale && width >= dst_lev->width)
       width = align(width, w_align);
@@ -661,6 +649,8 @@ etna_try_rs_blit(struct pipe_context *pctx,
        width & (w_align - 1) || height & (h_align - 1))
       goto manual;
 
+   mtx_lock(&ctx->lock);
+
    /* Always flush color and depth cache together before resolving. This works
     * around artifacts that appear in some cases when scanning out a texture
     * directly after it has been rendered to, such as rendering an animated web
@@ -750,6 +740,7 @@ etna_try_rs_blit(struct pipe_context *pctx,
    dst->seqno++;
    dst_lev->ts_valid = false;
    ctx->dirty |= ETNA_DIRTY_DERIVE_TS;
+   mtx_unlock(&ctx->lock);
 
    return true;