{"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"},
{"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
{"nir", ETNA_DBG_NIR, "use new NIR compiler"},
+ {"deqp", ETNA_DBG_DEQP, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */
DEBUG_NAMED_VALUE_END
};
{
struct etna_screen *screen = etna_screen(pscreen);
- _mesa_set_destroy(screen->used_resources, NULL);
- mtx_destroy(&screen->lock);
-
if (screen->perfmon)
etna_perfmon_del(screen->perfmon);
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
+ case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
return 1;
case PIPE_CAP_NATIVE_FENCE_FD:
return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
return 0;
/* Stream output. */
+ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
+ return DBG_ENABLED(ETNA_DBG_DEQP) ? 4 : 0;
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return 0;
return 128;
case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
return 255;
+ case PIPE_CAP_MAX_VERTEX_BUFFERS:
+ return screen->specs.stream_count;
+ case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
+ return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
+
/* Texturing. */
+ case PIPE_CAP_TEXTURE_SHADOW_MAP:
+ return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2;
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
+ case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */
return screen->specs.max_texture_size;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
{
int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
assert(log2_max_tex_size > 0);
return log2_max_tex_size;
}
- case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
- return 5;
+
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MIN_TEXEL_OFFSET:
return -8;
/* Preferences */
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return 0;
+ case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: {
+ /* etnaviv is being run on systems as small as 256MB total RAM so
+ * we need to provide a sane value for such a device. Limit the
+ * memory budget to min(~3% of pyhiscal memory, 64MB).
+ *
+ * a simple divison by 32 provides the numbers we want.
+ * 256MB / 32 = 8MB
+ * 2048MB / 32 = 64MB
+ */
+ uint64_t system_memory;
+
+ if (!os_get_total_physical_memory(&system_memory))
+ system_memory = 4096 << 20;
+
+ return MIN2(system_memory / 32, 64 * 1024 * 1024);
+ }
case PIPE_CAP_MAX_VARYINGS:
return screen->specs.max_varyings;
enum pipe_shader_cap param)
{
struct etna_screen *screen = etna_screen(pscreen);
+ bool ubo_enable = screen->specs.halti >= 2 && DBG_ENABLED(ETNA_DBG_NIR);
+
+ if (DBG_ENABLED(ETNA_DBG_DEQP))
+ ubo_enable = true;
switch (shader) {
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_CAP_MAX_TEMPS:
return 64; /* Max native temporaries. */
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return 1;
+ return ubo_enable ? ETNA_MAX_CONST_BUF : 1;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
- case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_FP16:
return 0;
+ case PIPE_SHADER_CAP_INTEGERS:
+ return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return shader == PIPE_SHADER_FRAGMENT
case PIPE_SHADER_CAP_PREFERRED_IR:
return DBG_ENABLED(ETNA_DBG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
- return 4096;
+ if (ubo_enable)
+ return 16384; /* 16384 so state tracker enables UBOs */
+ return shader == PIPE_SHADER_FRAGMENT
+ ? screen->specs.max_ps_uniforms * sizeof(float[4])
+ : screen->specs.max_vs_uniforms * sizeof(float[4]);
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
- case PIPE_SHADER_CAP_SCALAR_ISA:
return 0;
}
}
static bool
-gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
- enum pipe_format format)
+gpu_supports_texture_target(struct etna_screen *screen,
+ enum pipe_texture_target target)
+{
+ if (target == PIPE_TEXTURE_CUBE_ARRAY)
+ return false;
+
+ /* pre-halti has no array/3D */
+ if (screen->specs.halti < 0 &&
+ (target == PIPE_TEXTURE_1D_ARRAY ||
+ target == PIPE_TEXTURE_2D_ARRAY ||
+ target == PIPE_TEXTURE_3D))
+ return false;
+
+ return true;
+}
+
+static bool
+gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
+ enum pipe_format format)
{
bool supported = true;
supported = screen->specs.tex_astc;
}
+ if (util_format_is_snorm(format))
+ supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
+
+ if (format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
+ (util_format_is_pure_integer(format) || util_format_is_float(format)))
+ supported = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
+
+
if (!supported)
return false;
return true;
}
+static bool
+gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format,
+ unsigned sample_count)
+{
+ const uint32_t fmt = translate_pe_format(format);
+
+ if (fmt == ETNA_NO_MATCH)
+ return false;
+
+ /* Validate MSAA; number of samples must be allowed, and render target
+ * must have MSAA'able format. */
+ if (sample_count > 1) {
+ if (!VIV_FEATURE(screen, chipFeatures, MSAA))
+ return false;
+ if (!translate_samples_to_xyscale(sample_count, NULL, NULL))
+ return false;
+ if (translate_ts_format(format) == ETNA_NO_MATCH)
+ return false;
+ }
+
+ if (format == PIPE_FORMAT_R8_UNORM)
+ return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5);
+
+ /* figure out 8bpp RS clear to enable these formats */
+ if (format == PIPE_FORMAT_R8_SINT || format == PIPE_FORMAT_R8_UINT)
+ return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5);
+
+ if (util_format_is_srgb(format))
+ return VIV_FEATURE(screen, chipMinorFeatures5, HALTI3);
+
+ if (util_format_is_pure_integer(format) || util_format_is_float(format))
+ return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
+
+ if (format == PIPE_FORMAT_R8G8_UNORM)
+ return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
+
+ /* any other extended format is HALTI0 (only R10G10B10A2?) */
+ if (fmt >= PE_FORMAT_R16F)
+ return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
+
+ return true;
+}
+
+static bool
+gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format)
+{
+ if (translate_vertex_format_type(format) == ETNA_NO_MATCH)
+ return false;
+
+ if (util_format_is_pure_integer(format))
+ return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
+
+ return true;
+}
+
static bool
etna_screen_is_format_supported(struct pipe_screen *pscreen,
enum pipe_format format,
struct etna_screen *screen = etna_screen(pscreen);
unsigned allowed = 0;
- if (target != PIPE_BUFFER &&
- target != PIPE_TEXTURE_1D &&
- target != PIPE_TEXTURE_2D &&
- target != PIPE_TEXTURE_3D &&
- target != PIPE_TEXTURE_CUBE &&
- target != PIPE_TEXTURE_RECT)
+ if (!gpu_supports_texture_target(screen, target))
return false;
if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
return false;
if (usage & PIPE_BIND_RENDER_TARGET) {
- /* if render target, must be RS-supported format */
- if (translate_rs_format(format) != ETNA_NO_MATCH) {
- /* Validate MSAA; number of samples must be allowed, and render target
- * must have MSAA'able format. */
- if (sample_count > 1) {
- if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
- translate_ts_format(format) != ETNA_NO_MATCH) {
- allowed |= PIPE_BIND_RENDER_TARGET;
- }
- } else {
- allowed |= PIPE_BIND_RENDER_TARGET;
- }
- }
+ if (gpu_supports_render_format(screen, format, sample_count))
+ allowed |= PIPE_BIND_RENDER_TARGET;
}
if (usage & PIPE_BIND_DEPTH_STENCIL) {
if (usage & PIPE_BIND_SAMPLER_VIEW) {
uint32_t fmt = translate_texture_format(format);
- if (!gpu_supports_texure_format(screen, fmt, format))
+ if (!gpu_supports_texture_format(screen, fmt, format))
fmt = ETNA_NO_MATCH;
if (sample_count < 2 && fmt != ETNA_NO_MATCH)
}
if (usage & PIPE_BIND_VERTEX_BUFFER) {
- if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
+ if (gpu_supports_vertex_format(screen, format))
allowed |= PIPE_BIND_VERTEX_BUFFER;
}
*count = num_modifiers;
}
+static void
+etna_determine_uniform_limits(struct etna_screen *screen)
+{
+ /* values for the non unified case are taken from
+ * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
+ * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
+ */
+ if (screen->model == chipModel_GC2000 &&
+ (screen->revision == 0x5118 || screen->revision == 0x5140)) {
+ screen->specs.max_vs_uniforms = 256;
+ screen->specs.max_ps_uniforms = 64;
+ } else if (screen->specs.num_constants == 320) {
+ screen->specs.max_vs_uniforms = 256;
+ screen->specs.max_ps_uniforms = 64;
+ } else if (screen->specs.num_constants > 256 &&
+ screen->model == chipModel_GC1000) {
+ /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
+ screen->specs.max_vs_uniforms = 256;
+ screen->specs.max_ps_uniforms = 64;
+ } else if (screen->specs.num_constants > 256) {
+ screen->specs.max_vs_uniforms = 256;
+ screen->specs.max_ps_uniforms = 256;
+ } else if (screen->specs.num_constants == 256) {
+ screen->specs.max_vs_uniforms = 256;
+ screen->specs.max_ps_uniforms = 256;
+ } else {
+ screen->specs.max_vs_uniforms = 168;
+ screen->specs.max_ps_uniforms = 64;
+ }
+}
+
static bool
etna_get_specs(struct etna_screen *screen)
{
screen->specs.vertex_sampler_offset = 8;
screen->specs.fragment_sampler_count = 8;
screen->specs.vertex_sampler_count = 4;
+
+ if (screen->model == 0x400)
+ screen->specs.vertex_sampler_count = 0;
+
screen->specs.vs_need_z_div =
screen->model < 0x1000 && screen->model != 0x880;
screen->specs.has_sin_cos_sqrt =
if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
screen->specs.max_varyings = ETNA_NUM_VARYINGS;
- /* from QueryShaderCaps in kernel driver */
- if (screen->model < chipModel_GC4000) {
- screen->specs.max_vs_uniforms = 168;
- screen->specs.max_ps_uniforms = 64;
- } else {
- screen->specs.max_vs_uniforms = 256;
- screen->specs.max_ps_uniforms = 256;
- }
+ etna_determine_uniform_limits(screen);
if (screen->specs.halti >= 5) {
screen->specs.has_unified_uniforms = true;
if (screen->specs.single_buffer)
DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
- screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
+ screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC) &&
+ !VIV_FEATURE(screen, chipMinorFeatures6, NO_ASTC);
screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
if (!etna_get_specs(screen))
goto fail;
+ if (screen->specs.halti >= 5 && !etnaviv_device_softpin_capable(dev)) {
+ DBG("halti5 requires softpin");
+ goto fail;
+ }
+
screen->options = (nir_shader_compiler_options) {
.lower_fpow = true,
.lower_sub = true,
if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
etna_pm_query_setup(screen);
- mtx_init(&screen->lock, mtx_recursive);
- screen->used_resources = _mesa_set_create(NULL, _mesa_hash_pointer,
- _mesa_key_pointer_equal);
- if (!screen->used_resources)
- goto fail2;
-
return pscreen;
-fail2:
- mtx_destroy(&screen->lock);
fail:
etna_screen_destroy(pscreen);
return NULL;
projects / mesa.git / blobdiff