#include "state_tracker/drm_driver.h"
+#include <drm_fourcc.h>
+
#define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_BINDLESS_TEXTURE:
+ case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
+ case PIPE_CAP_QUERY_SO_OVERFLOW:
+ case PIPE_CAP_MEMOBJ:
+ case PIPE_CAP_LOAD_CONSTBUF:
return 0;
/* Stream output. */
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
case PIPE_SHADER_CAP_INTEGERS:
+ case PIPE_SHADER_CAP_INT64_ATOMICS:
+ case PIPE_SHADER_CAP_FP16:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
- if (fmt & EXT_FORMAT)
+ if (fmt & EXT_FORMAT) {
supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
- if (util_format_is_snorm(format))
- supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
+ /* ETC1 is checked above, as it has its own feature bit. ETC2 is
+ * supported with HALTI0, however that implementation is buggy in hardware.
+ * The blob driver does per-block patching to work around this. As this
+ * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
+ * only.
+ */
+ if (util_format_is_etc(format))
+ supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
+ }
if (!supported)
return false;
return usage == allowed;
}
+const uint64_t supported_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_VIVANTE_TILED,
+ DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
+ DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
+ DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
+};
+
+static void
+etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
+ enum pipe_format format, int max,
+ uint64_t *modifiers,
+ unsigned int *external_only, int *count)
+{
+ struct etna_screen *screen = etna_screen(pscreen);
+ int i, num_modifiers = 0;
+
+ if (max > ARRAY_SIZE(supported_modifiers))
+ max = ARRAY_SIZE(supported_modifiers);
+
+ if (!max) {
+ modifiers = NULL;
+ max = ARRAY_SIZE(supported_modifiers);
+ }
+
+ for (i = 0; num_modifiers < max; i++) {
+ /* don't advertise split tiled formats on single pipe/buffer GPUs */
+ if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
+ i >= 3)
+ break;
+
+ if (modifiers)
+ modifiers[num_modifiers] = supported_modifiers[i];
+ if (external_only)
+ external_only[num_modifiers] = 0;
+ num_modifiers++;
+ }
+
+ *count = num_modifiers;
+}
+
static boolean
etna_get_specs(struct etna_screen *screen)
{
screen->model >= 0x1000 || screen->model == 0x880;
screen->specs.npot_tex_any_wrap =
VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
- screen->specs.has_new_sin_cos =
+ screen->specs.has_new_transcendentals =
VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
* same.
*/
screen->specs.ps_offset = 0x8000 + 0x1000;
- screen->specs.max_instructions = 256;
+ screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
+ screen->specs.has_icache = true;
} else {
if (instruction_count > 256) { /* unified instruction memory? */
screen->specs.vs_offset = 0xC000;
screen->specs.ps_offset = 0x6000;
screen->specs.max_instructions = instruction_count / 2;
}
+ screen->specs.has_icache = false;
}
if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
screen->specs.max_vs_uniforms = 256;
screen->specs.max_ps_uniforms = 256;
}
+ /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
+ */
+ if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) {
+ screen->specs.has_unified_uniforms = true;
+ screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
+ /* hardcode PS uniforms to start after end of VS uniforms -
+ * for more flexibility this offset could be variable based on the
+ * shader.
+ */
+ screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
+ } else {
+ screen->specs.has_unified_uniforms = false;
+ screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
+ screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
+ }
screen->specs.max_texture_size =
VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
return false;
}
-boolean
-etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
- unsigned stride, struct winsys_handle *whandle)
-{
- whandle->stride = stride;
-
- if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
- return etna_bo_get_name(bo, &whandle->handle) == 0;
- } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
- whandle->handle = etna_bo_handle(bo);
- return TRUE;
- } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
- whandle->handle = etna_bo_dmabuf(bo);
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
struct etna_bo *
etna_screen_bo_from_handle(struct pipe_screen *pscreen,
struct winsys_handle *whandle, unsigned *out_stride)
pscreen->get_timestamp = etna_screen_get_timestamp;
pscreen->context_create = etna_context_create;
pscreen->is_format_supported = etna_screen_is_format_supported;
+ pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
etna_fence_screen_init(pscreen);
etna_query_screen_init(pscreen);
projects / mesa.git / blobdiff