cs->GL_VARYING_TOTAL_COMPONENTS =
VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(align(total_components, 2));
- cs->GL_VARYING_NUM_COMPONENTS = num_components[0];
+ cs->GL_VARYING_NUM_COMPONENTS[0] = num_components[0];
+ cs->GL_VARYING_NUM_COMPONENTS[1] = num_components[1];
cs->GL_VARYING_COMPONENT_USE[0] = component_use[0];
cs->GL_VARYING_COMPONENT_USE[1] = component_use[1];
cs->ps_inst_mem_size = fs->code_size;
cs->PS_INST_MEM = fs->code;
- if (vs->needs_icache | fs->needs_icache) {
+ if (vs->needs_icache || fs->needs_icache) {
/* If either of the shaders needs ICACHE, we use it for both. It is
* either switched on or off for the entire shader processor.
*/
etna_bitarray_set(vs_input, 8, idx, cur_temp++);
}
+ if (vs->vs_id_in_reg >= 0) {
+ cs->VS_INPUT_COUNT = VIVS_VS_INPUT_COUNT_COUNT(num_vs_inputs + 1) |
+ VIVS_VS_INPUT_COUNT_UNK8(vs->input_count_unk8) |
+ VIVS_VS_INPUT_COUNT_ID_ENABLE;
+
+ etna_bitarray_set(vs_input, 8, num_vs_inputs, vs->vs_id_in_reg);
+
+ cs->FE_HALTI5_ID_CONFIG =
+ VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE |
+ VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE |
+ VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(vs->vs_id_in_reg * 4) |
+ VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(vs->vs_id_in_reg * 4 + 1);
+ }
+
for (int idx = 0; idx < ARRAY_SIZE(cs->VS_INPUT); ++idx)
cs->VS_INPUT[idx] = vs_input[idx];
const struct pipe_shader_state *pss)
{
struct etna_context *ctx = etna_context(pctx);
+ struct etna_screen *screen = ctx->screen;
struct etna_shader *shader = CALLOC_STRUCT(etna_shader);
if (!shader)
static uint32_t id;
shader->id = id++;
- shader->specs = &ctx->specs;
+ shader->specs = &screen->specs;
if (DBG_ENABLED(ETNA_DBG_NIR))
shader->nir = (pss->type == PIPE_SHADER_IR_NIR) ? pss->ir.nir :