#include "util/u_inlines.h"
#include "util/u_math.h"
#include "util/u_memory.h"
+#include "util/u_upload_mgr.h"
static void
etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
ctx->stencil_ref_s = *sr;
- cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
- /* rest of bits weaved in from depth_stencil_alpha */
- cs->PE_STENCIL_CONFIG_EXT =
- VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
+ for (unsigned i = 0; i < 2; i++) {
+ cs->PE_STENCIL_CONFIG[i] =
+ VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
+ cs->PE_STENCIL_CONFIG_EXT[i] =
+ VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
+ }
ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
}
/* there is no support for ARB_uniform_buffer_object */
assert(cb->buffer == NULL && cb->user_buffer != NULL);
+ if (!cb->buffer) {
+ struct pipe_constant_buffer *cb = &ctx->constant_buffer[shader];
+ u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
+ }
+
ctx->dirty |= ETNA_DIRTY_CONSTBUF;
}
static void
-etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
+etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
{
- struct etna_resource *res = etna_resource(pres);
+ struct etna_resource *to = base, *from = base;
- if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
- /* The render buffer is older than the texture buffer. Copy it over. */
- etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
- res->seqno = etna_resource(res->texture)->seqno;
+ if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
+ from = etna_resource(base->texture);
+
+ if (base->render)
+ to = etna_resource(base->render);
+
+ if ((to != from) && etna_resource_older(to, from)) {
+ etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
+ to->seqno = from->seqno;
}
}
static void
etna_set_framebuffer_state(struct pipe_context *pctx,
- const struct pipe_framebuffer_state *sv)
+ const struct pipe_framebuffer_state *fb)
{
struct etna_context *ctx = etna_context(pctx);
struct compiled_framebuffer_state *cs = &ctx->framebuffer;
uint32_t ts_mem_config = 0;
uint32_t pe_mem_config = 0;
- if (sv->nr_cbufs > 0) { /* at least one color buffer? */
- struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
+ if (fb->nr_cbufs > 0) { /* at least one color buffer? */
+ struct etna_surface *cbuf = etna_surface(fb->cbufs[0]);
struct etna_resource *res = etna_resource(cbuf->base.texture);
bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
+ uint32_t fmt = translate_pe_format(cbuf->base.format);
assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
- etna_update_render_resource(pctx, cbuf->base.texture);
+ etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
+
+ if (fmt >= PE_FORMAT_R16F)
+ cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
+ VIVS_PE_COLOR_FORMAT_FORMAT_MASK;
+ else
+ cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
- cs->PE_COLOR_FORMAT =
- VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
+ cs->PE_COLOR_FORMAT |=
VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
VIVS_PE_COLOR_FORMAT_OVERWRITE |
COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
- }
- /* MSAA */
- if (cbuf->base.texture->nr_samples > 1) {
- ts_mem_config |=
- VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
- VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(translate_msaa_format(cbuf->base.format));
+ if (cbuf->level->ts_compress_fmt >= 0) {
+ /* overwrite bit breaks v1/v2 compression */
+ if (!ctx->specs.v4_compression)
+ cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
+
+ ts_mem_config |=
+ VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
+ VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
+ }
}
nr_samples_color = cbuf->base.texture->nr_samples;
cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
}
- if (sv->zsbuf != NULL) {
- struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
+ if (fb->zsbuf != NULL) {
+ struct etna_surface *zsbuf = etna_surface(fb->zsbuf);
struct etna_resource *res = etna_resource(zsbuf->base.texture);
- etna_update_render_resource(pctx, zsbuf->base.texture);
+ etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
depth_format |
COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
+ VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */
COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
;
/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
+
+ if (zsbuf->level->ts_compress_fmt >= 0) {
+ ts_mem_config |=
+ VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
+ COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
+ VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
+ }
}
ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
- /* MSAA */
- if (zsbuf->base.texture->nr_samples > 1)
- /* XXX VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
- * Disable without MSAA for now, as it causes corruption in glquake. */
- ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
-
nr_samples_depth = zsbuf->base.texture->nr_samples;
} else {
cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
/* Scissor setup */
cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
cs->SE_SCISSOR_TOP = 0;
- cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
- cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
- cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
- cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
+ cs->SE_SCISSOR_RIGHT = (fb->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
+ cs->SE_SCISSOR_BOTTOM = (fb->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
+ cs->SE_CLIP_RIGHT = (fb->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
+ cs->SE_CLIP_BOTTOM = (fb->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
cs->TS_MEM_CONFIG = ts_mem_config;
cs->PE_MEM_CONFIG = pe_mem_config;
cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
/* keep copy of original structure */
- util_copy_framebuffer_state(&ctx->framebuffer_s, sv);
+ util_copy_framebuffer_state(&ctx->framebuffer_s, fb);
ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
}