#include "hw/common.xml.h"
+#include "etnaviv_blend.h"
#include "etnaviv_clear_blit.h"
#include "etnaviv_context.h"
#include "etnaviv_format.h"
#include "util/u_math.h"
#include "util/u_memory.h"
-static void
-etna_set_blend_color(struct pipe_context *pctx, const struct pipe_blend_color *bc)
-{
- struct etna_context *ctx = etna_context(pctx);
- struct compiled_blend_color *cs = &ctx->blend_color;
-
- cs->PE_ALPHA_BLEND_COLOR =
- VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(bc->color[0])) |
- VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(bc->color[1])) |
- VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(bc->color[2])) |
- VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(bc->color[3]));
- ctx->dirty |= ETNA_DIRTY_BLEND_COLOR;
-}
-
static void
etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
{
}
static void
-etna_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
+etna_set_constant_buffer(struct pipe_context *pctx,
+ enum pipe_shader_type shader, uint index,
const struct pipe_constant_buffer *cb)
{
struct etna_context *ctx = etna_context(pctx);
cs->PE_COLOR_ADDR = cbuf->reloc[0];
cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
} else {
- /* Rendered textures must always be multi-tiled */
- assert(res->layout & ETNA_LAYOUT_BIT_MULTI);
+ /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
+ assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
/* Scissor setup */
cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
cs->SE_SCISSOR_TOP = 0;
- cs->SE_SCISSOR_RIGHT = (sv->width << 16) - 1;
- cs->SE_SCISSOR_BOTTOM = (sv->height << 16) - 1;
+ cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
+ cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
+ cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
+ cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
cs->TS_MEM_CONFIG = ts_mem_config;
+ /* Single buffer setup. There is only one switch for this, not a separate
+ * one per color buffer / depth buffer. To keep the logic simple always use
+ * single buffer when this feature is available.
+ */
+ cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 2 : 0);
+
ctx->framebuffer_s = *sv; /* keep copy of original structure */
ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER;
}
{
struct etna_context *ctx = etna_context(pctx);
struct compiled_scissor_state *cs = &ctx->scissor;
+ assert(ss->minx <= ss->maxx);
+ assert(ss->miny <= ss->maxy);
/* note that this state is only used when rasterizer_state->scissor is on */
ctx->scissor_s = *ss;
cs->SE_SCISSOR_LEFT = (ss->minx << 16);
cs->SE_SCISSOR_TOP = (ss->miny << 16);
- cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) - 1;
- cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) - 1;
+ cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
+ cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
+ cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
+ cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
ctx->dirty |= ETNA_DIRTY_SCISSOR;
}
/* Compute scissor rectangle (fixp) from viewport.
* Make sure left is always < right and top always < bottom.
*/
- cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - vs->scale[0], 0.0f));
- cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - vs->scale[1], 0.0f));
- cs->SE_SCISSOR_RIGHT = etna_f32_to_fixp16(MAX2(vs->translate[0] + vs->scale[0], 0.0f));
- cs->SE_SCISSOR_BOTTOM = etna_f32_to_fixp16(MAX2(vs->translate[1] + vs->scale[1], 0.0f));
-
- if (cs->SE_SCISSOR_LEFT > cs->SE_SCISSOR_RIGHT) {
- uint32_t tmp = cs->SE_SCISSOR_RIGHT;
- cs->SE_SCISSOR_RIGHT = cs->SE_SCISSOR_LEFT;
- cs->SE_SCISSOR_LEFT = tmp;
- }
-
- if (cs->SE_SCISSOR_TOP > cs->SE_SCISSOR_BOTTOM) {
- uint32_t tmp = cs->SE_SCISSOR_BOTTOM;
- cs->SE_SCISSOR_BOTTOM = cs->SE_SCISSOR_TOP;
- cs->SE_SCISSOR_TOP = tmp;
- }
+ cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
+ cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
+ uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
+ uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
+ cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
+ cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
+ cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
+ cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
cs->PE_DEPTH_FAR = fui(1.0);
struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
struct pipe_vertex_buffer *vbi = &so->vb[idx];
- assert(!vbi->user_buffer); /* XXX support user_buffer using
- etna_usermem_map */
+ assert(!vbi->is_user_buffer); /* XXX support user_buffer using
+ etna_usermem_map */
- if (vbi->buffer) { /* GPU buffer */
- cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer)->bo;
+ if (vbi->buffer.resource) { /* GPU buffer */
+ cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
cs->FE_VERTEX_STREAM_CONTROL =
ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
}
-static void
-etna_set_index_buffer(struct pipe_context *pctx, const struct pipe_index_buffer *ib)
-{
- struct etna_context *ctx = etna_context(pctx);
- uint32_t ctrl;
-
- if (ib) {
- pipe_resource_reference(&ctx->index_buffer.ib.buffer, ib->buffer);
- memcpy(&ctx->index_buffer.ib, ib, sizeof(ctx->index_buffer.ib));
- ctrl = translate_index_size(ctx->index_buffer.ib.index_size);
- } else {
- pipe_resource_reference(&ctx->index_buffer.ib.buffer, NULL);
- ctrl = 0;
- }
-
- if (ctx->index_buffer.ib.buffer && ctrl != ETNA_NO_MATCH) {
- ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = etna_resource(ctx->index_buffer.ib.buffer)->bo;
- ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.offset = ctx->index_buffer.ib.offset;
- ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
- ctx->index_buffer.FE_INDEX_STREAM_CONTROL = ctrl;
- } else {
- ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = NULL;
- ctx->index_buffer.FE_INDEX_STREAM_CONTROL = 0;
- }
-
- ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
-}
-
static void
etna_blend_state_bind(struct pipe_context *pctx, void *bs)
{
},
{
etna_shader_link, ETNA_DIRTY_SHADER,
+ },
+ {
+ etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
+ },
+ {
+ etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
}
};
pctx->set_viewport_states = etna_set_viewport_states;
pctx->set_vertex_buffers = etna_set_vertex_buffers;
- pctx->set_index_buffer = etna_set_index_buffer;
pctx->bind_blend_state = etna_blend_state_bind;
pctx->delete_blend_state = etna_blend_state_delete;
projects / mesa.git / blobdiff