radeonsi: stop using TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS

[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_zsa.c

diff --git a/src/gallium/drivers/etnaviv/etnaviv_zsa.c b/src/gallium/drivers/etnaviv/etnaviv_zsa.c
index a677e2555f094862fddbbc59246a451d69b6f84a..7cac316c1da79047492f6db2d9f342970f75eafe 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_zsa.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_zsa.c
@@ -29,6 +29,7 @@
 #include "etnaviv_context.h"
 #include "etnaviv_screen.h"
 #include "etnaviv_translate.h"
+#include "util/u_half.h"
 #include "util/u_memory.h"
 
 #include "hw/common.xml.h"
@@ -38,6 +39,7 @@ etna_zsa_state_create(struct pipe_context *pctx,
                       const struct pipe_depth_stencil_alpha_state *so)
 {
    struct etna_context *ctx = etna_context(pctx);
+   struct etna_screen *screen = ctx->screen;
    struct etna_zsa_state *cs = CALLOC_STRUCT(etna_zsa_state);
 
    if (!cs)
@@ -92,6 +94,15 @@ etna_zsa_state_create(struct pipe_context *pctx,
    if (so->depth.enabled == false || so->depth.func == PIPE_FUNC_ALWAYS)
       early_z = false;
 
+   /* calculate extra_reference value */
+   uint32_t extra_reference = 0;
+
+   if (VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT))
+      extra_reference = util_float_to_half(SATURATE(so->alpha.ref_value));
+
+   cs->PE_STENCIL_CONFIG_EXT =
+      VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(extra_reference);
+
    /* compare funcs have 1 to 1 mapping */
    cs->PE_DEPTH_CONFIG =
       VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(so->depth.enabled ? so->depth.func
@@ -99,31 +110,40 @@ etna_zsa_state_create(struct pipe_context *pctx,
       COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
       COND(early_z, VIVS_PE_DEPTH_CONFIG_EARLY_Z) |
       /* this bit changed meaning with HALTI5: */
-      COND(disable_zs && ctx->specs.halti < 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
+      COND((disable_zs && screen->specs.halti < 5) || ((early_z || disable_zs) && VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH)), VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
+
    cs->PE_ALPHA_OP =
       COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) |
       VIVS_PE_ALPHA_OP_ALPHA_FUNC(so->alpha.func) |
       VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(so->alpha.ref_value));
 
    for (unsigned i = 0; i < 2; i++) {
+      const struct pipe_stencil_state *stencil_front = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[i] : &so->stencil[0];
+      const struct pipe_stencil_state *stencil_back = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[!i] : &so->stencil[0];
       cs->PE_STENCIL_OP[i] =
-         VIVS_PE_STENCIL_OP_FUNC_FRONT(so->stencil[i].func) |
-         VIVS_PE_STENCIL_OP_FUNC_BACK(so->stencil[!i].func) |
-         VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(so->stencil[i].fail_op)) |
-         VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(so->stencil[!i].fail_op)) |
-         VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(so->stencil[i].zfail_op)) |
-         VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(so->stencil[!i].zfail_op)) |
-         VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(so->stencil[i].zpass_op)) |
-         VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(so->stencil[!i].zpass_op));
+         VIVS_PE_STENCIL_OP_FUNC_FRONT(stencil_front->func) |
+         VIVS_PE_STENCIL_OP_FUNC_BACK(stencil_back->func) |
+         VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(stencil_front->fail_op)) |
+         VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(stencil_back->fail_op)) |
+         VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(stencil_front->zfail_op)) |
+         VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(stencil_back->zfail_op)) |
+         VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(stencil_front->zpass_op)) |
+         VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(stencil_back->zpass_op));
       cs->PE_STENCIL_CONFIG[i] =
-         translate_stencil_mode(so->stencil[i].enabled, so->stencil[!i].enabled) |
-         VIVS_PE_STENCIL_CONFIG_MASK_FRONT(so->stencil[i].valuemask) |
-         VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so->stencil[i].writemask);
+         translate_stencil_mode(so->stencil[0].enabled, so->stencil[0].enabled) |
+         VIVS_PE_STENCIL_CONFIG_MASK_FRONT(stencil_front->valuemask) |
+         VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(stencil_front->writemask);
       cs->PE_STENCIL_CONFIG_EXT2[i] =
-         VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(so->stencil[!i].valuemask) |
-         VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(so->stencil[!i].writemask);
+         VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(stencil_back->valuemask) |
+         VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(stencil_back->writemask);
    }
 
+   /* blob sets this to 0x40000031 on GC7000, seems to make no difference,
+    * but keep it in mind if depth behaves strangely. */
+   cs->RA_DEPTH_CONFIG = 0x00000031;
+   if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH) && !disable_zs && !early_z)
+      cs->RA_DEPTH_CONFIG |= 0x11000000;
+
    /* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */
    return cs;
 }