git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 26087 bytes, from 2017-10-30 13:44:54)
-- common.xml ( 26187 bytes, from 2017-10-31 19:05:01)
-- common_3d.xml ( 14615 bytes, from 2017-11-04 14:03:35)
-- state_hi.xml ( 27733 bytes, from 2017-10-02 19:00:30)
-- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
-- state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml ( 79992 bytes, from 2017-11-07 10:44:35)
-- state_blt.xml ( 13405 bytes, from 2017-10-16 17:42:46)
-- state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22)
-
-Copyright (C) 2012-2017 by the following authors:
+- state.xml ( 26877 bytes, from 2020-02-14 10:19:56)
+- common.xml ( 35468 bytes, from 2020-01-04 20:02:31)
+- common_3d.xml ( 15058 bytes, from 2020-04-17 16:31:50)
+- state_hi.xml ( 34851 bytes, from 2020-04-17 16:25:34)
+- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
+- state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26)
+- state_3d.xml ( 83771 bytes, from 2020-04-17 17:15:55)
+- state_blt.xml ( 14252 bytes, from 2020-01-10 14:36:29)
+- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26)
+
+Copyright (C) 2012-2020 by the following authors:
- Wladimir J. van der Laan <laanwj@gmail.com>
- Christian Gmeiner <christian.gmeiner@gmail.com>
- Lucas Stach <l.stach@pengutronix.de>
*/
-#define COMPARE_FUNC_NEVER 0x00000000
-#define COMPARE_FUNC_LESS 0x00000001
-#define COMPARE_FUNC_EQUAL 0x00000002
-#define COMPARE_FUNC_LEQUAL 0x00000003
-#define COMPARE_FUNC_GREATER 0x00000004
-#define COMPARE_FUNC_NOTEQUAL 0x00000005
-#define COMPARE_FUNC_GEQUAL 0x00000006
-#define COMPARE_FUNC_ALWAYS 0x00000007
#define STENCIL_OP_KEEP 0x00000000
#define STENCIL_OP_ZERO 0x00000001
#define STENCIL_OP_REPLACE 0x00000002
#define RS_FORMAT_X8R8G8B8 0x00000005
#define RS_FORMAT_A8R8G8B8 0x00000006
#define RS_FORMAT_YUY2 0x00000007
-#define RS_FORMAT_A8 0x00000010
-#define RS_FORMAT_R16F 0x00000011
-#define RS_FORMAT_G16R16F 0x00000012
-#define RS_FORMAT_A16B16G16R16F 0x00000013
-#define RS_FORMAT_R32F 0x00000014
-#define RS_FORMAT_G32R32F 0x00000015
-#define RS_FORMAT_A2B10G10R10 0x00000016
-#define RS_FORMAT_R8I 0x00000017
-#define RS_FORMAT_G8R8I 0x00000018
-#define RS_FORMAT_A8B8G8R8I 0x00000019
-#define RS_FORMAT_R16I 0x0000001a
-#define RS_FORMAT_G16R16I 0x0000001b
-#define RS_FORMAT_A16B16G16R16I 0x0000001c
-#define RS_FORMAT_B10G11R11F 0x0000001d
-#define RS_FORMAT_A2B10G10R10UI 0x0000001e
-#define RS_FORMAT_G8R8 0x0000001f
-#define RS_FORMAT_R8 0x00000023
+#define RS_FORMAT_64BPP_CLEAR 0x00000015
+#define PE_FORMAT_X4R4G4B4 0x00000000
+#define PE_FORMAT_A4R4G4B4 0x00000001
+#define PE_FORMAT_X1R5G5B5 0x00000002
+#define PE_FORMAT_A1R5G5B5 0x00000003
+#define PE_FORMAT_R5G6B5 0x00000004
+#define PE_FORMAT_X8R8G8B8 0x00000005
+#define PE_FORMAT_A8R8G8B8 0x00000006
+#define PE_FORMAT_YUY2 0x00000007
+#define PE_FORMAT_A8 0x00000010
+#define PE_FORMAT_R16F 0x00000011
+#define PE_FORMAT_G16R16F 0x00000012
+#define PE_FORMAT_A16B16G16R16F 0x00000013
+#define PE_FORMAT_R32F 0x00000014
+#define PE_FORMAT_G32R32F 0x00000015
+#define PE_FORMAT_A2B10G10R10 0x00000016
+#define PE_FORMAT_R8I 0x00000017
+#define PE_FORMAT_G8R8I 0x00000018
+#define PE_FORMAT_A8B8G8R8I 0x00000019
+#define PE_FORMAT_R16I 0x0000001a
+#define PE_FORMAT_G16R16I 0x0000001b
+#define PE_FORMAT_A16B16G16R16I 0x0000001c
+#define PE_FORMAT_B10G11R11F 0x0000001d
+#define PE_FORMAT_A2B10G10R10UI 0x0000001e
+#define PE_FORMAT_G8R8 0x0000001f
+#define PE_FORMAT_R8 0x00000023
#define LOGIC_OP_CLEAR 0x00000000
#define LOGIC_OP_NOR 0x00000001
#define LOGIC_OP_AND_INVERTED 0x00000002
#define LOGIC_OP_OR_REVERSE 0x0000000d
#define LOGIC_OP_OR 0x0000000e
#define LOGIC_OP_SET 0x0000000f
-#define TS_SAMPLER_FORMAT_A4R4G4B4 0x00000000
-#define TS_SAMPLER_FORMAT_A1R5G5B5 0x00000001
-#define TS_SAMPLER_FORMAT_R5G6B5 0x00000002
-#define TS_SAMPLER_FORMAT_A8R8G8B8 0x00000003
-#define TS_SAMPLER_FORMAT_X8R8G8B8 0x00000004
-#define TS_SAMPLER_FORMAT_D24X8 0x00000005
-#define TS_SAMPLER_FORMAT_D16 0x00000008
-#define TS_SAMPLER_FORMAT_RAW 0x0000000f
+#define COLOR_OUTPUT_MODE_NORMAL 0x00000000
+#define COLOR_OUTPUT_MODE_A2B10G10R10UI 0x00000001
+#define COLOR_OUTPUT_MODE_UIF32 0x00000002
+#define COLOR_OUTPUT_MODE_U8 0x00000003
+#define COLOR_OUTPUT_MODE_U16 0x00000004
+#define COLOR_OUTPUT_MODE_I8 0x00000005
+#define COLOR_OUTPUT_MODE_I16 0x00000006
#define VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007
#define VARYING_NUM_COMPONENTS_VAR0__SHIFT 0
#define VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK)
#define VIVS_VS_INPUT_COUNT_UNK8__MASK 0x00001f00
#define VIVS_VS_INPUT_COUNT_UNK8__SHIFT 8
#define VIVS_VS_INPUT_COUNT_UNK8(x) (((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK)
+#define VIVS_VS_INPUT_COUNT_ID_ENABLE 0x80000000
#define VIVS_VS_TEMP_REGISTER_CONTROL 0x0000080c
#define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f
#define VIVS_PS_CONTROL 0x00001010
#define VIVS_PS_CONTROL_BYPASS 0x00000001
-#define VIVS_PS_CONTROL_UNK1 0x00000002
+#define VIVS_PS_CONTROL_SATURATE_RT0 0x00000002
+#define VIVS_PS_CONTROL_SATURATE_RT1 0x00000004
+#define VIVS_PS_CONTROL_SATURATE_RT2 0x00000008
+#define VIVS_PS_CONTROL_SATURATE_RT3 0x00000010
+#define VIVS_PS_CONTROL_RT_COUNT__MASK 0x00000700
+#define VIVS_PS_CONTROL_RT_COUNT__SHIFT 8
+#define VIVS_PS_CONTROL_RT_COUNT(x) (((x) << VIVS_PS_CONTROL_RT_COUNT__SHIFT) & VIVS_PS_CONTROL_RT_COUNT__MASK)
#define VIVS_PS_PERF_COUNTER 0x00001014
#define VIVS_PS_INST_ADDR 0x00001028
-#define VIVS_PS_UNK0102C 0x0000102c
+#define VIVS_PS_CONTROL2 0x0000102c
+#define VIVS_PS_CONTROL2_SATURATE_RT4 0x00000080
+#define VIVS_PS_CONTROL2_SATURATE_RT5 0x00008000
+#define VIVS_PS_CONTROL2_SATURATE_RT6 0x00800000
+#define VIVS_PS_CONTROL2_SATURATE_RT7 0x80000000
#define VIVS_PS_CONTROL_EXT 0x00001030
-#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK 0x00000003
-#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT 0
-#define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT(x) (((x) << VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT) & VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK 0x00000007
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT 0
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK 0x00000070
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT 4
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK 0x00000700
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT 8
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK 0x00007000
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT 12
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK 0x00070000
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT 16
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK 0x00700000
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT 20
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK 0x07000000
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT 24
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK)
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK 0x70000000
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT 28
+#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK)
#define VIVS_PS_UNK01034 0x00001034
#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK)
#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK 0x00000100
#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK 0x00000200
-#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK 0xffff0000
-#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT 16
-#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK)
+#define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK 0xffff0000
+#define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT 16
+#define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK)
#define VIVS_PE_LOGIC_OP 0x000014a4
#define VIVS_PE_LOGIC_OP_OP__MASK 0x0000000f
#define VIVS_PE_LOGIC_OP_OP__SHIFT 0
#define VIVS_PE_LOGIC_OP_OP(x) (((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK)
#define VIVS_PE_LOGIC_OP_OP_MASK 0x00000010
+#define VIVS_PE_LOGIC_OP_DITHER_MODE__MASK 0x00000060
+#define VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT 5
+#define VIVS_PE_LOGIC_OP_DITHER_MODE(x) (((x) << VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT) & VIVS_PE_LOGIC_OP_DITHER_MODE__MASK)
#define VIVS_PE_LOGIC_OP_SINGLE_BUFFER_MASK 0x00000080
#define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK 0x00000300
#define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT 8
#define VIVS_PE_LOGIC_OP_SINGLE_BUFFER(x) (((x) << VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT) & VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK)
-#define VIVS_PE_LOGIC_OP_UNK11_MASK 0x00000400
+#define VIVS_PE_LOGIC_OP_DITHER_MODE_MASK 0x00000400
#define VIVS_PE_LOGIC_OP_UNK11 0x00000800
#define VIVS_PE_LOGIC_OP_UNK20__MASK 0x00300000
#define VIVS_PE_LOGIC_OP_UNK20__SHIFT 20
#define VIVS_PE_LOGIC_OP_UNK24__SHIFT 24
#define VIVS_PE_LOGIC_OP_UNK24(x) (((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK)
#define VIVS_PE_LOGIC_OP_UNK24_MASK 0x08000000
-#define VIVS_PE_LOGIC_OP_UNK31_MASK 0x40000000
-#define VIVS_PE_LOGIC_OP_UNK31 0x80000000
+#define VIVS_PE_LOGIC_OP_SRGB_MASK 0x40000000
+#define VIVS_PE_LOGIC_OP_SRGB 0x80000000
#define VIVS_PE_DITHER(i0) (0x000014a8 + 0x4*(i0))
#define VIVS_PE_DITHER__ESIZE 0x00000004
#define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK)
#define VIVS_PE_MEM_CONFIG 0x000014bc
-#define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__MASK 0x01000000
-#define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__SHIFT 24
-#define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__MASK)
-#define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__MASK 0x04000000
-#define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__SHIFT 26
-#define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__MASK)
+#define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK 0x01000000
+#define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT 24
+#define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK)
+#define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK 0x04000000
+#define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT 26
+#define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK)
#define VIVS_PE_HALTI4_UNK014C0 0x000014c0
#define VIVS_PE_RT_CONFIG_STRIDE__MASK 0x0000ffff
#define VIVS_PE_RT_CONFIG_STRIDE__SHIFT 0
#define VIVS_PE_RT_CONFIG_STRIDE(x) (((x) << VIVS_PE_RT_CONFIG_STRIDE__SHIFT) & VIVS_PE_RT_CONFIG_STRIDE__MASK)
-#define VIVS_PE_RT_CONFIG_UNK16__MASK 0xffff0000
-#define VIVS_PE_RT_CONFIG_UNK16__SHIFT 16
-#define VIVS_PE_RT_CONFIG_UNK16(x) (((x) << VIVS_PE_RT_CONFIG_UNK16__SHIFT) & VIVS_PE_RT_CONFIG_UNK16__MASK)
+#define VIVS_PE_RT_CONFIG_FORMAT__MASK 0x001f0000
+#define VIVS_PE_RT_CONFIG_FORMAT__SHIFT 16
+#define VIVS_PE_RT_CONFIG_FORMAT(x) (((x) << VIVS_PE_RT_CONFIG_FORMAT__SHIFT) & VIVS_PE_RT_CONFIG_FORMAT__MASK)
+#define VIVS_PE_RT_CONFIG_SUPER_TILED 0x04000000
+#define VIVS_PE_RT_CONFIG_UNK28 0x10000000
#define VIVS_PE_HALTI5_UNK14920(i0) (0x00014920 + 0x4*(i0))
#define VIVS_PE_HALTI5_UNK14920__ESIZE 0x00000004
#define VIVS_PE_HALTI5_UNK14920__LEN 0x00000007
+#define VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK 0x000000f0
+#define VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT 4
+#define VIVS_PE_HALTI5_UNK14920_COMPONENTS(x) (((x) << VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT) & VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK)
+#define VIVS_PE_HALTI5_UNK14920_UNK8 0x00000100
#define VIVS_PE_HALTI5_UNK14940(i0) (0x00014940 + 0x4*(i0))
#define VIVS_PE_HALTI5_UNK14940__ESIZE 0x00000004
#define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK 0x0003ffff
#define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT 0
#define VIVS_RS_SOURCE_STRIDE_STRIDE(x) (((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK)
+#define VIVS_RS_SOURCE_STRIDE_UNK29 0x20000000
#define VIVS_RS_SOURCE_STRIDE_MULTI 0x40000000
#define VIVS_RS_SOURCE_STRIDE_TILING 0x80000000
#define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK)
#define VIVS_TS_MEM_CONFIG_UNK12 0x00001000
#define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE 0x00002000
-#define VIVS_TS_MEM_CONFIG_UNK14 0x00004000
+#define VIVS_TS_MEM_CONFIG_STENCIL_ENABLE 0x00004000
#define VIVS_TS_MEM_CONFIG_UNK21 0x00200000
#define VIVS_TS_COLOR_STATUS_BASE 0x00001658
#define VIVS_TS_SAMPLER__LEN 0x00000008
#define VIVS_TS_SAMPLER_CONFIG(i0) (0x00001720 + 0x4*(i0))
-#define VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK 0x00000003
-#define VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT 0
-#define VIVS_TS_SAMPLER_CONFIG_ENABLE(x) (((x) << VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT) & VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK)
-#define VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK 0x000000f0
-#define VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT 4
-#define VIVS_TS_SAMPLER_CONFIG_FORMAT(x) (((x) << VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK)
+#define VIVS_TS_SAMPLER_CONFIG_ENABLE 0x00000001
+#define VIVS_TS_SAMPLER_CONFIG_COMPRESSION 0x00000002
+#define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK 0x000000f0
+#define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT 4
+#define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK)
#define VIVS_TS_SAMPLER_CONFIG_UNK11__MASK 0x00003800
#define VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT 11
#define VIVS_TS_SAMPLER_CONFIG_UNK11(x) (((x) << VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT) & VIVS_TS_SAMPLER_CONFIG_UNK11__MASK)
#define VIVS_YUV 0x00000000
-#define VIVS_YUV_UNK01678 0x00001678
+#define VIVS_YUV_CONFIG 0x00001678
+#define VIVS_YUV_CONFIG_ENABLE 0x00000001
+#define VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK 0x00000030
+#define VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT 4
+#define VIVS_YUV_CONFIG_SOURCE_FORMAT(x) (((x) << VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK)
+#define VIVS_YUV_CONFIG_UV_SWAP 0x00000100
-#define VIVS_YUV_UNK0167C 0x0000167c
+#define VIVS_YUV_WINDOW_SIZE 0x0000167c
+#define VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK 0xffff0000
+#define VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT 16
+#define VIVS_YUV_WINDOW_SIZE_HEIGHT(x) (((x) << VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK)
+#define VIVS_YUV_WINDOW_SIZE_WIDTH__MASK 0x0000ffff
+#define VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT 0
+#define VIVS_YUV_WINDOW_SIZE_WIDTH(x) (((x) << VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_YUV_WINDOW_SIZE_WIDTH__MASK)
-#define VIVS_YUV_UNK01680 0x00001680
+#define VIVS_YUV_Y_BASE 0x00001680
-#define VIVS_YUV_UNK01684 0x00001684
+#define VIVS_YUV_Y_STRIDE 0x00001684
-#define VIVS_YUV_UNK01688 0x00001688
+#define VIVS_YUV_U_BASE 0x00001688
-#define VIVS_YUV_UNK0168C 0x0000168c
+#define VIVS_YUV_U_STRIDE 0x0000168c
-#define VIVS_YUV_UNK01690 0x00001690
+#define VIVS_YUV_V_BASE 0x00001690
-#define VIVS_YUV_UNK01694 0x00001694
+#define VIVS_YUV_V_STRIDE 0x00001694
-#define VIVS_YUV_UNK01698 0x00001698
+#define VIVS_YUV_DEST_BASE 0x00001698
-#define VIVS_YUV_UNK0169C 0x0000169c
+#define VIVS_YUV_DEST_STRIDE 0x0000169c
#define VIVS_TE 0x00000000
#define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT 13
#define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK)
#define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV 0x00080000
+#define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK 0x00300000
+#define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT 20
+#define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK)
#define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000
#define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22
#define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK)
#define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10
#define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
#define VIVS_TE_SAMPLER_LOG_SIZE_ASTC 0x10000000
-#define VIVS_TE_SAMPLER_LOG_SIZE_RGB 0x20000000
+#define VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000
#define VIVS_TE_SAMPLER_LOG_SIZE_SRGB 0x80000000
#define VIVS_TE_SAMPLER_LOD_CONFIG(i0) (0x000020c0 + 0x4*(i0))
#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000
#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20
#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
-#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__MASK 0x00800000
-#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT 23
-#define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK 0x00800000
+#define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT 23
+#define VIVS_TE_SAMPLER_CONFIG1_TS_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK)
#define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000
-#define VIVS_TE_SAMPLER_CONFIG1_UNK25 0x02000000
+#define VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP 0x02000000
#define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000
#define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT 26
#define VIVS_TE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK)
#define VIVS_TE_SAMPLER_UNK02240(i0) (0x00002240 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_ASTC0(i0) (0x00002280 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x0000000f
+#define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0
+#define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK)
+#define VIVS_TE_SAMPLER_ASTC0_ASTC_SRGB 0x00000010
+#define VIVS_TE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00
+#define VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT 8
+#define VIVS_TE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK8__MASK)
+#define VIVS_TE_SAMPLER_ASTC0_UNK16__MASK 0x00ff0000
+#define VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT 16
+#define VIVS_TE_SAMPLER_ASTC0_UNK16(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK16__MASK)
+#define VIVS_TE_SAMPLER_ASTC0_UNK24__MASK 0xff000000
+#define VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT 24
+#define VIVS_TE_SAMPLER_ASTC0_UNK24(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK24__MASK)
+
+#define VIVS_TE_SAMPLER_ASTC1(i0) (0x00002300 + 0x4*(i0))
+
+#define VIVS_TE_SAMPLER_ASTC2(i0) (0x00002380 + 0x4*(i0))
+
+#define VIVS_TE_SAMPLER_ASTC3(i0) (0x00002340 + 0x4*(i0))
+
#define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1) (0x00002400 + 0x4*(i0) + 0x40*(i1))
#define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE 0x00000040
#define VIVS_TE_SAMPLER_LOD_ADDR__LEN 0x0000000e
#define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT 13
#define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK)
#define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV 0x00080000
+#define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK 0x00300000
+#define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT 20
+#define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK)
#define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000
#define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22
#define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK)
#define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10
#define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
#define VIVS_NTE_SAMPLER_LOG_SIZE_ASTC 0x10000000
-#define VIVS_NTE_SAMPLER_LOG_SIZE_RGB 0x20000000
+#define VIVS_NTE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000
#define VIVS_NTE_SAMPLER_LOG_SIZE_SRGB 0x80000000
#define VIVS_NTE_SAMPLER_LOD_CONFIG(i0) (0x00010180 + 0x4*(i0))
#define VIVS_NTE_SAMPLER_UNK10200(i0) (0x00010200 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_UNK10280(i0) (0x00010280 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_LINEAR_STRIDE(i0, i1) (0x00010280 + 0x4*(i0) + 0x4*(i1))
+#define VIVS_NTE_SAMPLER_LINEAR_STRIDE__ESIZE 0x00000004
+#define VIVS_NTE_SAMPLER_LINEAR_STRIDE__LEN 0x00000020
#define VIVS_NTE_SAMPLER_3D_CONFIG(i0) (0x00010300 + 0x4*(i0))
#define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff
#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000
#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20
#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
-#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__MASK 0x00800000
-#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT 23
-#define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK 0x00800000
+#define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT 23
+#define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK)
#define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000
-#define VIVS_NTE_SAMPLER_CONFIG1_UNK25 0x02000000
+#define VIVS_NTE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP 0x02000000
#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000
#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT 26
#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK)
#define VIVS_NTE_SAMPLER_UNK10480(i0) (0x00010480 + 0x4*(i0))
#define VIVS_NTE_SAMPLER_ASTC0(i0) (0x00010500 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x000000ff
+#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x0000000f
#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0
#define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK)
+#define VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB 0x00000010
#define VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00
#define VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT 8
#define VIVS_NTE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK)
#define VIVS_NTE_SAMPLER_ASTC2(i0) (0x00010600 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010600 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010680 + 0x4*(i0))
#define VIVS_NTE_SAMPLER_BASELOD(i0) (0x00010700 + 0x4*(i0))
-#define VIVS_NTE_SAMPLER_BASELOD_UNK23 0x00800000
#define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK 0x0000000f
#define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT 0
#define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK)
#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK 0x00000f00
#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT 8
#define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK)
+#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE 0x00010000
+#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK 0x00700000
+#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT 20
+#define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK)
+#define VIVS_NTE_SAMPLER_BASELOD_BASELOD_ENABLE 0x00800000
#define VIVS_NTE_SAMPLER_UNK10780(i0) (0x00010780 + 0x4*(i0))
#define VIVS_NTE_DESCRIPTOR_ADDR(i0) (0x00015c00 + 0x4*(i0))
#define VIVS_NTE_DESCRIPTOR_TX_CTRL(i0) (0x00015e00 + 0x4*(i0))
-#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK 0x00000003
-#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT 0
-#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK)
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK 0x00000001
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT 0
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK)
+#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE 0x00000002
#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK 0x0000001c
#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT 2
#define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK)
#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0) (0x00016600 + 0x4*(i0))
-#define VIVS_NTE_DESCRIPTOR_UNK17400_MIRROR(i0) (0x00016800 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY_MIRROR(i0) (0x00016800 + 0x4*(i0))
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0) (0x00016c00 + 0x4*(i0))
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK 0x00000007
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK 0x00006000
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT 13
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK)
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_ENABLE 0x00020000
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK 0x001c0000
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT 18
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK)
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21 0x00200000
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22 0x00400000
-#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_RGB 0x00800000
+#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_INT_FILTER 0x00800000
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0) (0x00016e00 + 0x4*(i0))
#define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1 0x00000002
#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK)
#define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE 0x00010000
-#define VIVS_NTE_DESCRIPTOR_UNK17400(i0) (0x00017400 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY(i0) (0x00017400 + 0x4*(i0))
#define VIVS_SH 0x00000000
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