freedreno: a2xx: fix clear color

[mesa.git] / src / gallium / drivers / freedreno / a2xx / fd2_emit.c

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
index d749eb0324a9c2fc178dc9680d7c7080dd4385c9..dcf7ed10b545220f82fcf2a83f157cd618f56041 100644 (file)
--- a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
@@ -295,7 +295,7 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
        if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
                OUT_PKT3(ring, CP_SET_CONSTANT, 2);
                OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
-               OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol);
+               OUT_RING(ring, blend ? zsa->rb_colorcontrol | blend->rb_colorcontrol : 0);
        }
 
        if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
@@ -305,13 +305,13 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
 
                OUT_PKT3(ring, CP_SET_CONSTANT, 2);
                OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
-               OUT_RING(ring, blend->rb_blendcontrol_alpha |
+               OUT_RING(ring, blend ? blend->rb_blendcontrol_alpha |
                        COND(has_alpha, blend->rb_blendcontrol_rgb) |
-                       COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb));
+                       COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb) : 0);
 
                OUT_PKT3(ring, CP_SET_CONSTANT, 2);
                OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
-               OUT_RING(ring, blend->rb_colormask);
+               OUT_RING(ring, blend ? blend->rb_colormask : 0xf);
        }
 
        if (dirty & FD_DIRTY_BLEND_COLOR) {
@@ -332,6 +332,16 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
 void
 fd2_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring)
 {
+       if (is_a20x(ctx->screen)) {
+               OUT_PKT0(ring, REG_A2XX_RB_BC_CONTROL, 1);
+               OUT_RING(ring,
+                       A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(3) |
+                       A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP |
+                       A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE |
+                       A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(8) |
+                       A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(3));
+       }
+
        OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1);
        OUT_RING(ring, 0x00000002);