#include "instr-a3xx.h"
#include "ir-a3xx.h"
-/* ************************************************************************* */
-/* split the out or find some helper to use.. like main/bitset.h.. */
-
-#define MAX_REG 256
-
-typedef uint8_t regmask_t[2 * MAX_REG / 8];
-
-static unsigned regmask_idx(struct ir3_register *reg)
-{
- unsigned num = reg->num;
- assert(num < MAX_REG);
- if (reg->flags & IR3_REG_HALF)
- num += MAX_REG;
- return num;
-}
-
-static void regmask_set(regmask_t regmask, struct ir3_register *reg)
-{
- unsigned idx = regmask_idx(reg);
- regmask[idx / 8] |= 1 << (idx % 8);
-}
-
-static unsigned regmask_get(regmask_t regmask, struct ir3_register *reg)
-{
- unsigned idx = regmask_idx(reg);
- return regmask[idx / 8] & (1 << (idx % 8));
-}
-
-/* ************************************************************************* */
struct fd3_compile_context {
const struct tgsi_token *tokens;
/* last input dst (for setting (ei) flag): */
struct ir3_register *last_input;
+ /* last instruction with relative addressing: */
+ struct ir3_instruction *last_rel;
+
+ /* for calculating input/output positions/linkages: */
unsigned next_inloc;
+
unsigned num_internal_temps;
+ struct tgsi_src_register internal_temps[6];
/* track registers which need to synchronize w/ "complex alu" cat3
* instruction pipeline:
* up the vector operation
*/
struct tgsi_dst_register tmp_dst;
- struct tgsi_src_register tmp_src;
+ struct tgsi_src_register *tmp_src;
};
+
+static void vectorize(struct fd3_compile_context *ctx,
+ struct ir3_instruction *instr, struct tgsi_dst_register *dst,
+ int nsrcs, ...);
+static void create_mov(struct fd3_compile_context *ctx,
+ struct tgsi_dst_register *dst, struct tgsi_src_register *src);
+
static unsigned
compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
const struct tgsi_token *tokens)
{
- unsigned ret;
+ unsigned ret, base = 0;
+ struct tgsi_shader_info *info = &ctx->info;
ctx->tokens = tokens;
ctx->ir = so->ir;
ctx->so = so;
ctx->last_input = NULL;
+ ctx->last_rel = NULL;
ctx->next_inloc = 8;
ctx->num_internal_temps = 0;
ctx->branch_count = 0;
- memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
- memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
+ regmask_init(&ctx->needs_ss);
+ regmask_init(&ctx->needs_sy);
memset(ctx->base_reg, 0, sizeof(ctx->base_reg));
tgsi_scan_shader(tokens, &ctx->info);
/* Immediates go after constants: */
ctx->base_reg[TGSI_FILE_CONSTANT] = 0;
ctx->base_reg[TGSI_FILE_IMMEDIATE] =
- ctx->info.file_count[TGSI_FILE_CONSTANT];
+ info->file_max[TGSI_FILE_CONSTANT] + 1;
+
+ /* if full precision and fragment shader, don't clobber
+ * r0.x w/ bary fetch:
+ */
+ if ((so->type == SHADER_FRAGMENT) && !so->half_precision)
+ base = 1;
/* Temporaries after outputs after inputs: */
- ctx->base_reg[TGSI_FILE_INPUT] = 0;
- ctx->base_reg[TGSI_FILE_OUTPUT] =
- ctx->info.file_count[TGSI_FILE_INPUT];
- ctx->base_reg[TGSI_FILE_TEMPORARY] =
- ctx->info.file_count[TGSI_FILE_INPUT] +
- ctx->info.file_count[TGSI_FILE_OUTPUT];
+ ctx->base_reg[TGSI_FILE_INPUT] = base;
+ ctx->base_reg[TGSI_FILE_OUTPUT] = base +
+ info->file_max[TGSI_FILE_INPUT] + 1;
+ ctx->base_reg[TGSI_FILE_TEMPORARY] = base +
+ info->file_max[TGSI_FILE_INPUT] + 1 +
+ info->file_max[TGSI_FILE_OUTPUT] + 1;
so->first_immediate = ctx->base_reg[TGSI_FILE_IMMEDIATE];
- ctx->immediate_idx = 4 * (ctx->info.file_count[TGSI_FILE_CONSTANT] +
- ctx->info.file_count[TGSI_FILE_IMMEDIATE]);
+ ctx->immediate_idx = 4 * (ctx->info.file_max[TGSI_FILE_IMMEDIATE] + 1);
ret = tgsi_parse_init(&ctx->parser, tokens);
if (ret != TGSI_PARSE_OK)
return ret;
}
+static void
+compile_error(struct fd3_compile_context *ctx, const char *format, ...)
+{
+ va_list ap;
+ va_start(ap, format);
+ _debug_vprintf(format, ap);
+ va_end(ap);
+ tgsi_dump(ctx->tokens, 0);
+ assert(0);
+}
+
+#define compile_assert(ctx, cond) do { \
+ if (!(cond)) compile_error((ctx), "failed assert: "#cond"\n"); \
+ } while (0)
+
static void
compile_free(struct fd3_compile_context *ctx)
{
unsigned arg;
};
+static void
+handle_last_rel(struct fd3_compile_context *ctx)
+{
+ if (ctx->last_rel) {
+ ctx->last_rel->flags |= IR3_INSTR_UL;
+ ctx->last_rel = NULL;
+ }
+}
+
+static void
+add_nop(struct fd3_compile_context *ctx, unsigned count)
+{
+ while (count-- > 0)
+ ir3_instr_create(ctx->ir, 0, OPC_NOP);
+}
+
+static unsigned
+src_flags(struct fd3_compile_context *ctx, struct ir3_register *reg)
+{
+ unsigned flags = 0;
+
+ if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED))
+ return flags;
+
+ if (regmask_get(&ctx->needs_ss, reg)) {
+ flags |= IR3_INSTR_SS;
+ regmask_init(&ctx->needs_ss);
+ }
+
+ if (regmask_get(&ctx->needs_sy, reg)) {
+ flags |= IR3_INSTR_SY;
+ regmask_init(&ctx->needs_sy);
+ }
+
+ return flags;
+}
+
static struct ir3_register *
add_dst_reg(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
const struct tgsi_dst_register *dst, unsigned chan)
case TGSI_FILE_TEMPORARY:
num = dst->Index + ctx->base_reg[dst->File];
break;
+ case TGSI_FILE_ADDRESS:
+ num = REG_A0;
+ break;
default:
- DBG("unsupported dst register file: %s",
+ compile_error(ctx, "unsupported dst register file: %s\n",
tgsi_file_name(dst->File));
- assert(0);
break;
}
unsigned flags = 0, num = 0;
struct ir3_register *reg;
+ /* TODO we need to use a mov to temp for const >= 64.. or maybe
+ * we could use relative addressing..
+ */
+ compile_assert(ctx, src->Index < 64);
+
switch (src->File) {
case TGSI_FILE_IMMEDIATE:
/* TODO if possible, use actual immediate instead of const.. but
flags |= IR3_REG_CONST;
num = src->Index + ctx->base_reg[src->File];
break;
+ case TGSI_FILE_OUTPUT:
+ /* NOTE: we should only end up w/ OUTPUT file for things like
+ * clamp()'ing saturated dst instructions
+ */
case TGSI_FILE_INPUT:
case TGSI_FILE_TEMPORARY:
num = src->Index + ctx->base_reg[src->File];
break;
default:
- DBG("unsupported src register file: %s",
+ compile_error(ctx, "unsupported src register file: %s\n",
tgsi_file_name(src->File));
- assert(0);
break;
}
flags |= IR3_REG_ABS;
if (src->Negate)
flags |= IR3_REG_NEGATE;
+ if (src->Indirect)
+ flags |= IR3_REG_RELATIV;
if (ctx->so->half_precision)
flags |= IR3_REG_HALF;
reg = ir3_reg_create(instr, regid(num, chan), flags);
- if (regmask_get(ctx->needs_ss, reg)) {
- instr->flags |= IR3_INSTR_SS;
- memset(ctx->needs_ss, 0, sizeof(ctx->needs_ss));
- }
+ if (src->Indirect)
+ ctx->last_rel = instr;
- if (regmask_get(ctx->needs_sy, reg)) {
- instr->flags |= IR3_INSTR_SY;
- memset(ctx->needs_sy, 0, sizeof(ctx->needs_sy));
- }
+ instr->flags |= src_flags(ctx, reg);
return reg;
}
/* Get internal-temp src/dst to use for a sequence of instructions
* generated by a single TGSI op.
*/
-static void
+static struct tgsi_src_register *
get_internal_temp(struct fd3_compile_context *ctx,
- struct tgsi_dst_register *tmp_dst,
- struct tgsi_src_register *tmp_src)
+ struct tgsi_dst_register *tmp_dst)
{
+ struct tgsi_src_register *tmp_src;
int n;
tmp_dst->File = TGSI_FILE_TEMPORARY;
/* assign next temporary: */
n = ctx->num_internal_temps++;
+ compile_assert(ctx, n < ARRAY_SIZE(ctx->internal_temps));
+ tmp_src = &ctx->internal_temps[n];
- tmp_dst->Index = ctx->info.file_count[TGSI_FILE_TEMPORARY] + n;
+ tmp_dst->Index = ctx->info.file_max[TGSI_FILE_TEMPORARY] + n + 1;
src_from_dst(tmp_src, tmp_dst);
+
+ return tmp_src;
}
-/* same as get_internal_temp, but w/ src.xxxx (for instructions that
- * replicate their results)
+/* Get internal half-precision temp src/dst to use for a sequence of
+ * instructions generated by a single TGSI op.
*/
-static void
-get_internal_temp_repl(struct fd3_compile_context *ctx,
- struct tgsi_dst_register *tmp_dst,
- struct tgsi_src_register *tmp_src)
+static struct tgsi_src_register *
+get_internal_temp_hr(struct fd3_compile_context *ctx,
+ struct tgsi_dst_register *tmp_dst)
{
- get_internal_temp(ctx, tmp_dst, tmp_src);
- tmp_src->SwizzleX = tmp_src->SwizzleY =
- tmp_src->SwizzleZ = tmp_src->SwizzleW = TGSI_SWIZZLE_X;
+ struct tgsi_src_register *tmp_src;
+ int n;
+
+ if (ctx->so->half_precision)
+ return get_internal_temp(ctx, tmp_dst);
+
+ tmp_dst->File = TGSI_FILE_TEMPORARY;
+ tmp_dst->WriteMask = TGSI_WRITEMASK_XYZW;
+ tmp_dst->Indirect = 0;
+ tmp_dst->Dimension = 0;
+
+ /* assign next temporary: */
+ n = ctx->num_internal_temps++;
+ compile_assert(ctx, n < ARRAY_SIZE(ctx->internal_temps));
+ tmp_src = &ctx->internal_temps[n];
+
+ /* just use hr0 because no one else should be using half-
+ * precision regs:
+ */
+ tmp_dst->Index = 0;
+
+ src_from_dst(tmp_src, tmp_dst);
+
+ return tmp_src;
+}
+
+static inline bool
+is_const(struct tgsi_src_register *src)
+{
+ return (src->File == TGSI_FILE_CONSTANT) ||
+ (src->File == TGSI_FILE_IMMEDIATE);
+}
+
+static inline bool
+is_relative(struct tgsi_src_register *src)
+{
+ return src->Indirect;
+}
+
+static inline bool
+is_rel_or_const(struct tgsi_src_register *src)
+{
+ return is_relative(src) || is_const(src);
+}
+
+static type_t
+get_ftype(struct fd3_compile_context *ctx)
+{
+ return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
+}
+
+static type_t
+get_utype(struct fd3_compile_context *ctx)
+{
+ return ctx->so->half_precision ? TYPE_U16 : TYPE_U32;
+}
+
+static unsigned
+src_swiz(struct tgsi_src_register *src, int chan)
+{
+ switch (chan) {
+ case 0: return src->SwizzleX;
+ case 1: return src->SwizzleY;
+ case 2: return src->SwizzleZ;
+ case 3: return src->SwizzleW;
+ }
+ assert(0);
+ return 0;
+}
+
+/* for instructions that cannot take a const register as src, if needed
+ * generate a move to temporary gpr:
+ */
+static struct tgsi_src_register *
+get_unconst(struct fd3_compile_context *ctx, struct tgsi_src_register *src)
+{
+ struct tgsi_dst_register tmp_dst;
+ struct tgsi_src_register *tmp_src;
+
+ compile_assert(ctx, is_rel_or_const(src));
+
+ tmp_src = get_internal_temp(ctx, &tmp_dst);
+
+ create_mov(ctx, &tmp_dst, src);
+
+ return tmp_src;
}
static void
reg->SwizzleW = swiz2tgsi[swiz];
}
-static type_t
-get_type(struct fd3_compile_context *ctx)
-{
- return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
-}
-
-static unsigned
-src_swiz(struct tgsi_src_register *src, int chan)
-{
- switch (chan) {
- case 0: return src->SwizzleX;
- case 1: return src->SwizzleY;
- case 2: return src->SwizzleZ;
- case 3: return src->SwizzleW;
- }
- assert(0);
- return 0;
-}
-
static void
create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
struct tgsi_src_register *src)
{
- type_t type_mov = get_type(ctx);
+ type_t type_mov = get_ftype(ctx);
unsigned i;
for (i = 0; i < 4; i++) {
/* move to destination: */
if (dst->WriteMask & (1 << i)) {
- struct ir3_instruction *instr =
- ir3_instr_create(ctx->ir, 1, 0);
- instr->cat1.src_type = type_mov;
- instr->cat1.dst_type = type_mov;
+ struct ir3_instruction *instr;
+
+ if (src->Absolute || src->Negate) {
+ /* can't have abs or neg on a mov instr, so use
+ * absneg.f instead to handle these cases:
+ */
+ instr = ir3_instr_create(ctx->ir, 2, OPC_ABSNEG_F);
+ } else {
+ instr = ir3_instr_create(ctx->ir, 1, 0);
+ instr->cat1.src_type = type_mov;
+ instr->cat1.dst_type = type_mov;
+ }
+
add_dst_reg(ctx, instr, dst, i);
add_src_reg(ctx, instr, src, src_swiz(src, i));
} else {
- ir3_instr_create(ctx->ir, 0, OPC_NOP);
+ add_nop(ctx, 1);
}
}
+}
+
+static void
+create_clamp(struct fd3_compile_context *ctx,
+ struct tgsi_dst_register *dst, struct tgsi_src_register *val,
+ struct tgsi_src_register *minval, struct tgsi_src_register *maxval)
+{
+ struct ir3_instruction *instr;
+
+ instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
+ vectorize(ctx, instr, dst, 2, val, 0, minval, 0);
+
+ instr = ir3_instr_create(ctx->ir, 2, OPC_MIN_F);
+ vectorize(ctx, instr, dst, 2, val, 0, maxval, 0);
+}
+
+static void
+create_clamp_imm(struct fd3_compile_context *ctx,
+ struct tgsi_dst_register *dst,
+ uint32_t minval, uint32_t maxval)
+{
+ struct tgsi_src_register minconst, maxconst;
+ struct tgsi_src_register src;
+
+ src_from_dst(&src, dst);
+ get_immediate(ctx, &minconst, minval);
+ get_immediate(ctx, &maxconst, maxval);
+
+ create_clamp(ctx, dst, &src, &minconst, &maxconst);
}
static struct tgsi_dst_register *
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
struct tgsi_src_register *src = &inst->Src[i].Register;
if ((src->File == dst->File) && (src->Index == dst->Index)) {
- get_internal_temp(ctx, &ctx->tmp_dst, &ctx->tmp_src);
+ if ((dst->WriteMask == TGSI_WRITEMASK_XYZW) &&
+ (src->SwizzleX == TGSI_SWIZZLE_X) &&
+ (src->SwizzleY == TGSI_SWIZZLE_Y) &&
+ (src->SwizzleZ == TGSI_SWIZZLE_Z) &&
+ (src->SwizzleW == TGSI_SWIZZLE_W))
+ continue;
+ ctx->tmp_src = get_internal_temp(ctx, &ctx->tmp_dst);
ctx->tmp_dst.WriteMask = dst->WriteMask;
dst = &ctx->tmp_dst;
break;
{
/* if necessary, add mov back into original dst: */
if (dst != &inst->Dst[0].Register) {
- create_mov(ctx, &inst->Dst[0].Register, &ctx->tmp_src);
+ create_mov(ctx, &inst->Dst[0].Register, ctx->tmp_src);
}
}
{
va_list ap;
int i, j, n = 0;
+ bool indirect = dst->Indirect;
- add_dst_reg(ctx, instr, dst, 0);
+ add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_X);
va_start(ap, nsrcs);
for (j = 0; j < nsrcs; j++) {
struct tgsi_src_register *src =
va_arg(ap, struct tgsi_src_register *);
unsigned flags = va_arg(ap, unsigned);
- add_src_reg(ctx, instr, src, 0)->flags |= flags;
+ struct ir3_register *reg;
+ if (flags & IR3_REG_IMMED) {
+ reg = ir3_reg_create(instr, 0, IR3_REG_IMMED);
+ /* this is an ugly cast.. should have put flags first! */
+ reg->iim_val = *(int *)&src;
+ } else {
+ reg = add_src_reg(ctx, instr, src, TGSI_SWIZZLE_X);
+ indirect |= src->Indirect;
+ }
+ reg->flags |= flags & ~IR3_REG_NEGATE;
+ if (flags & IR3_REG_NEGATE)
+ reg->flags ^= IR3_REG_NEGATE;
}
va_end(ap);
for (j = 0; j < nsrcs; j++) {
struct tgsi_src_register *src =
va_arg(ap, struct tgsi_src_register *);
- (void)va_arg(ap, unsigned);
- cur->regs[j+1]->num =
- regid(cur->regs[j+1]->num >> 2,
- src_swiz(src, i));
+ unsigned flags = va_arg(ap, unsigned);
+ if (!(flags & IR3_REG_IMMED)) {
+ cur->regs[j+1]->num =
+ regid(cur->regs[j+1]->num >> 2,
+ src_swiz(src, i));
+ cur->flags |= src_flags(ctx, cur->regs[j+1]);
+ }
}
va_end(ap);
+
+ if (indirect)
+ ctx->last_rel = cur;
}
}
/* pad w/ nop's.. at least until we are clever enough to
* figure out if we really need to..
*/
- for (; n < 4; n++) {
- ir3_instr_create(instr->shader, 0, OPC_NOP);
- }
+ add_nop(ctx, 4 - n);
}
/*
*/
static void
-trans_dotp(const struct instr_translater *t,
+trans_clamp(const struct instr_translater *t,
struct fd3_compile_context *ctx,
struct tgsi_full_instruction *inst)
{
- struct ir3_instruction *instr;
- struct tgsi_dst_register tmp_dst;
- struct tgsi_src_register tmp_src;
- struct tgsi_dst_register *dst = &inst->Dst[0].Register;
+ struct tgsi_dst_register *dst = get_dst(ctx, inst);
struct tgsi_src_register *src0 = &inst->Src[0].Register;
struct tgsi_src_register *src1 = &inst->Src[1].Register;
- unsigned swiz0[] = { src0->SwizzleX, src0->SwizzleY, src0->SwizzleZ, src0->SwizzleW };
- unsigned swiz1[] = { src1->SwizzleX, src1->SwizzleY, src1->SwizzleZ, src1->SwizzleW };
- opc_t opc_mad = ctx->so->half_precision ? OPC_MAD_F16 : OPC_MAD_F32;
- unsigned n = t->arg; /* number of components */
- unsigned i;
-
- get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
-
- /* Blob compiler never seems to use a const in src1 position for
- * mad.*, although there does seem (according to disassembler
- * hidden in libllvm-a3xx.so) to be a bit to indicate that src1
- * is a const. Not sure if this is a hw bug, or simply that the
- * disassembler lies.
- */
- if ((src1->File == TGSI_FILE_IMMEDIATE) ||
- (src1->File == TGSI_FILE_CONSTANT)) {
-
- /* the mov to tmp unswizzles src1, so now we have tmp.xyzw:
- */
- for (i = 0; i < 4; i++)
- swiz1[i] = i;
-
- /* the first mul.f will clobber tmp.x, but that is ok
- * because after that point we no longer need tmp.x:
- */
- create_mov(ctx, &tmp_dst, src1);
- src1 = &tmp_src;
- }
-
- instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
- add_dst_reg(ctx, instr, &tmp_dst, 0);
- add_src_reg(ctx, instr, src0, swiz0[0]);
- add_src_reg(ctx, instr, src1, swiz1[0]);
-
- for (i = 1; i < n; i++) {
- ir3_instr_create(ctx->ir, 0, OPC_NOP);
-
- instr = ir3_instr_create(ctx->ir, 3, opc_mad);
- add_dst_reg(ctx, instr, &tmp_dst, 0);
- add_src_reg(ctx, instr, src0, swiz0[i]);
- add_src_reg(ctx, instr, src1, swiz1[i]);
- add_src_reg(ctx, instr, &tmp_src, 0);
- }
-
- /* DPH(a,b) = (a.x * b.x) + (a.y * b.y) + (a.z * b.z) + b.w */
- if (t->tgsi_opc == TGSI_OPCODE_DPH) {
- ir3_instr_create(ctx->ir, 0, OPC_NOP);
-
- instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
- add_dst_reg(ctx, instr, &tmp_dst, 0);
- add_src_reg(ctx, instr, src1, swiz1[i]);
- add_src_reg(ctx, instr, &tmp_src, 0);
-
- n++;
- }
-
- ir3_instr_create(ctx->ir, 0, OPC_NOP);
-
- /* pad out to multiple of 4 scalar instructions: */
- for (i = 2 * n; i % 4; i++) {
- ir3_instr_create(ctx->ir, 0, OPC_NOP);
- }
+ struct tgsi_src_register *src2 = &inst->Src[2].Register;
- create_mov(ctx, dst, &tmp_src);
-}
-
-/* LRP(a,b,c) = (a * b) + ((1 - a) * c) */
-static void
-trans_lrp(const struct instr_translater *t,
- struct fd3_compile_context *ctx,
- struct tgsi_full_instruction *inst)
-{
- struct ir3_instruction *instr;
- struct tgsi_dst_register tmp_dst1, tmp_dst2;
- struct tgsi_src_register tmp_src1, tmp_src2;
- struct tgsi_src_register tmp_const;
-
- get_internal_temp(ctx, &tmp_dst1, &tmp_src1);
- get_internal_temp(ctx, &tmp_dst2, &tmp_src2);
-
- get_immediate(ctx, &tmp_const, fui(1.0));
-
- /* tmp1 = (a * b) */
- instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
- vectorize(ctx, instr, &tmp_dst1, 2,
- &inst->Src[0].Register, 0,
- &inst->Src[1].Register, 0);
-
- /* tmp2 = (1 - a) */
- instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
- vectorize(ctx, instr, &tmp_dst2, 2,
- &tmp_const, 0,
- &inst->Src[0].Register, IR3_REG_NEGATE);
-
- /* tmp2 = tmp2 * c */
- instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
- vectorize(ctx, instr, &tmp_dst2, 2,
- &tmp_src2, 0,
- &inst->Src[2].Register, 0);
+ create_clamp(ctx, dst, src0, src1, src2);
- /* dst = tmp1 + tmp2 */
- instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
- vectorize(ctx, instr, &inst->Dst[0].Register, 2,
- &tmp_src1, 0,
- &tmp_src2, 0);
+ put_dst(ctx, inst, dst);
}
-/* FRC(x) = x - FLOOR(x) */
+/* ARL(x) = x, but mova from hrN.x to a0.. */
static void
-trans_frac(const struct instr_translater *t,
+trans_arl(const struct instr_translater *t,
struct fd3_compile_context *ctx,
struct tgsi_full_instruction *inst)
{
struct ir3_instruction *instr;
struct tgsi_dst_register tmp_dst;
- struct tgsi_src_register tmp_src;
+ struct tgsi_src_register *tmp_src;
+ struct tgsi_dst_register *dst = &inst->Dst[0].Register;
+ struct tgsi_src_register *src = &inst->Src[0].Register;
+ unsigned chan = src->SwizzleX;
+ compile_assert(ctx, dst->File == TGSI_FILE_ADDRESS);
- get_internal_temp(ctx, &tmp_dst, &tmp_src);
+ handle_last_rel(ctx);
- /* tmp = FLOOR(x) */
- instr = ir3_instr_create(ctx->ir, 2, OPC_FLOOR_F);
- vectorize(ctx, instr, &tmp_dst, 1,
- &inst->Src[0].Register, 0);
+ tmp_src = get_internal_temp_hr(ctx, &tmp_dst);
- /* dst = x - tmp */
- instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
- vectorize(ctx, instr, &inst->Dst[0].Register, 2,
- &inst->Src[0].Register, 0,
- &tmp_src, IR3_REG_NEGATE);
-}
+ /* cov.{f32,f16}s16 Rtmp, Rsrc */
+ instr = ir3_instr_create(ctx->ir, 1, 0);
+ instr->cat1.src_type = get_ftype(ctx);
+ instr->cat1.dst_type = TYPE_S16;
+ add_dst_reg(ctx, instr, &tmp_dst, chan)->flags |= IR3_REG_HALF;
+ add_src_reg(ctx, instr, src, chan);
-/* POW(a,b) = EXP2(b * LOG2(a)) */
-static void
-trans_pow(const struct instr_translater *t,
- struct fd3_compile_context *ctx,
- struct tgsi_full_instruction *inst)
-{
- struct ir3_instruction *instr;
- struct ir3_register *r;
- struct tgsi_dst_register tmp_dst;
- struct tgsi_src_register tmp_src;
- struct tgsi_dst_register *dst = &inst->Dst[0].Register;
- struct tgsi_src_register *src0 = &inst->Src[0].Register;
- struct tgsi_src_register *src1 = &inst->Src[1].Register;
-
- get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
+ add_nop(ctx, 3);
- /* log2 Rtmp, Rsrc0 */
- ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
- instr = ir3_instr_create(ctx->ir, 4, OPC_LOG2);
- r = add_dst_reg(ctx, instr, &tmp_dst, 0);
- add_src_reg(ctx, instr, src0, src0->SwizzleX);
- regmask_set(ctx->needs_ss, r);
+ /* shl.b Rtmp, Rtmp, 2 */
+ instr = ir3_instr_create(ctx->ir, 2, OPC_SHL_B);
+ add_dst_reg(ctx, instr, &tmp_dst, chan)->flags |= IR3_REG_HALF;
+ add_src_reg(ctx, instr, tmp_src, chan)->flags |= IR3_REG_HALF;
+ ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = 2;
- /* mul.f Rtmp, Rtmp, Rsrc1 */
- instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
- add_dst_reg(ctx, instr, &tmp_dst, 0);
- add_src_reg(ctx, instr, &tmp_src, 0);
- add_src_reg(ctx, instr, src1, src1->SwizzleX);
-
- /* blob compiler seems to ensure there are at least 6 instructions
- * between a "simple" (non-cat4) instruction and a dependent cat4..
- * probably we need to handle this in some other places too.
- */
- ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
+ add_nop(ctx, 3);
- /* exp2 Rdst, Rtmp */
- instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
- r = add_dst_reg(ctx, instr, &tmp_dst, 0);
- add_src_reg(ctx, instr, &tmp_src, 0);
- regmask_set(ctx->needs_ss, r);
+ /* mova a0, Rtmp */
+ instr = ir3_instr_create(ctx->ir, 1, 0);
+ instr->cat1.src_type = TYPE_S16;
+ instr->cat1.dst_type = TYPE_S16;
+ add_dst_reg(ctx, instr, dst, 0)->flags |= IR3_REG_HALF;
+ add_src_reg(ctx, instr, tmp_src, chan)->flags |= IR3_REG_HALF;
- create_mov(ctx, dst, &tmp_src);
+ /* need to ensure 5 instr slots before a0 is used: */
+ add_nop(ctx, 6);
}
/* texture fetch/sample instructions: */
{
struct ir3_register *r;
struct ir3_instruction *instr;
- struct tgsi_dst_register tmp_dst;
- struct tgsi_src_register tmp_src;
struct tgsi_src_register *coord = &inst->Src[0].Register;
struct tgsi_src_register *samp = &inst->Src[1].Register;
unsigned tex = inst->Texture.Texture;
int8_t *order;
- unsigned i, j, flags = 0;
+ unsigned i, flags = 0, src_wrmask;
+ bool needs_mov = false;
switch (t->arg) {
case TGSI_OPCODE_TEX:
- order = (tex == TGSI_TEXTURE_2D) ?
- (int8_t[4]){ 0, 1, -1, -1 } : /* 2D */
- (int8_t[4]){ 0, 1, 2, -1 }; /* 3D */
+ if (tex == TGSI_TEXTURE_2D) {
+ order = (int8_t[4]){ 0, 1, -1, -1 };
+ src_wrmask = TGSI_WRITEMASK_XY;
+ } else {
+ order = (int8_t[4]){ 0, 1, 2, -1 };
+ src_wrmask = TGSI_WRITEMASK_XYZ;
+ }
break;
case TGSI_OPCODE_TXP:
- order = (tex == TGSI_TEXTURE_2D) ?
- (int8_t[4]){ 0, 1, 3, -1 } : /* 2D */
- (int8_t[4]){ 0, 1, 2, 3 }; /* 3D */
+ if (tex == TGSI_TEXTURE_2D) {
+ order = (int8_t[4]){ 0, 1, 3, -1 };
+ src_wrmask = TGSI_WRITEMASK_XYZ;
+ } else {
+ order = (int8_t[4]){ 0, 1, 2, 3 };
+ src_wrmask = TGSI_WRITEMASK_XYZW;
+ }
flags |= IR3_INSTR_P;
break;
default:
- assert(0);
+ compile_assert(ctx, 0);
break;
}
- if (tex == TGSI_TEXTURE_3D)
+ if ((tex == TGSI_TEXTURE_3D) || (tex == TGSI_TEXTURE_CUBE)) {
+ add_nop(ctx, 3);
flags |= IR3_INSTR_3D;
+ }
+
+ /* cat5 instruction cannot seem to handle const or relative: */
+ if (is_rel_or_const(coord))
+ needs_mov = true;
/* The texture sample instructions need to coord in successive
* registers/components (ie. src.xy but not src.yx). And TXP
* might need to emit some mov instructions to shuffle things
* around:
*/
- for (i = 1; (i < 4) && (order[i] >= 0); i++) {
- if (src_swiz(coord, i) != (src_swiz(coord, 0) + order[i])) {
- type_t type_mov = get_type(ctx);
+ for (i = 1; (i < 4) && (order[i] >= 0) && !needs_mov; i++)
+ if (src_swiz(coord, i) != (src_swiz(coord, 0) + order[i]))
+ needs_mov = true;
- /* need to move things around: */
- get_internal_temp(ctx, &tmp_dst, &tmp_src);
+ if (needs_mov) {
+ struct tgsi_dst_register tmp_dst;
+ struct tgsi_src_register *tmp_src;
+ unsigned j;
- for (j = 0; (j < 4) && (order[j] >= 0); j++) {
- instr = ir3_instr_create(ctx->ir, 1, 0);
- instr->cat1.src_type = type_mov;
- instr->cat1.dst_type = type_mov;
- add_dst_reg(ctx, instr, &tmp_dst, j);
- add_src_reg(ctx, instr, coord,
- src_swiz(coord, order[j]));
- }
+ type_t type_mov = get_ftype(ctx);
- coord = &tmp_src;
+ /* need to move things around: */
+ tmp_src = get_internal_temp(ctx, &tmp_dst);
- if (j < 4)
- ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 4 - j - 1;
-
- break;
+ for (j = 0; (j < 4) && (order[j] >= 0); j++) {
+ instr = ir3_instr_create(ctx->ir, 1, 0);
+ instr->cat1.src_type = type_mov;
+ instr->cat1.dst_type = type_mov;
+ add_dst_reg(ctx, instr, &tmp_dst, j);
+ add_src_reg(ctx, instr, coord,
+ src_swiz(coord, order[j]));
}
+
+ coord = tmp_src;
+
+ add_nop(ctx, 4 - j);
}
instr = ir3_instr_create(ctx->ir, 5, t->opc);
- instr->cat5.type = get_type(ctx);
+ instr->cat5.type = get_ftype(ctx);
instr->cat5.samp = samp->Index;
instr->cat5.tex = samp->Index;
instr->flags |= flags;
r = add_dst_reg(ctx, instr, &inst->Dst[0].Register, 0);
r->wrmask = inst->Dst[0].Register.WriteMask;
- add_src_reg(ctx, instr, coord, coord->SwizzleX);
+ add_src_reg(ctx, instr, coord, coord->SwizzleX)->wrmask = src_wrmask;
- regmask_set(ctx->needs_sy, r);
+ /* after add_src_reg() so we don't set (sy) on sam instr itself! */
+ regmask_set(&ctx->needs_sy, r);
}
-/* CMP(a,b,c) = (a < 0) ? b : c */
+/*
+ * SEQ(a,b) = (a == b) ? 1.0 : 0.0
+ * cmps.f.eq tmp0, b, a
+ * cov.u16f16 dst, tmp0
+ *
+ * SNE(a,b) = (a != b) ? 1.0 : 0.0
+ * cmps.f.eq tmp0, b, a
+ * add.s tmp0, tmp0, -1
+ * sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
+ * SGE(a,b) = (a >= b) ? 1.0 : 0.0
+ * cmps.f.ge tmp0, a, b
+ * cov.u16f16 dst, tmp0
+ *
+ * SLE(a,b) = (a <= b) ? 1.0 : 0.0
+ * cmps.f.ge tmp0, b, a
+ * cov.u16f16 dst, tmp0
+ *
+ * SGT(a,b) = (a > b) ? 1.0 : 0.0
+ * cmps.f.ge tmp0, b, a
+ * add.s tmp0, tmp0, -1
+ * sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
+ * SLT(a,b) = (a < b) ? 1.0 : 0.0
+ * cmps.f.ge tmp0, a, b
+ * add.s tmp0, tmp0, -1
+ * sel.f16 dst, {0.0}, tmp0, {1.0}
+ *
+ * CMP(a,b,c) = (a < 0.0) ? b : c
+ * cmps.f.ge tmp0, a, {0.0}
+ * add.s tmp0, tmp0, -1
+ * sel.f16 dst, c, tmp0, b
+ */
static void
trans_cmp(const struct instr_translater *t,
struct fd3_compile_context *ctx,
{
struct ir3_instruction *instr;
struct tgsi_dst_register tmp_dst;
- struct tgsi_src_register tmp_src;
- struct tgsi_src_register constval;
- /* final instruction uses original src1 and src2, so we need get_dst() */
+ struct tgsi_src_register *tmp_src;
+ struct tgsi_src_register constval0, constval1;
+ /* final instruction for CMP() uses orig src1 and src2: */
struct tgsi_dst_register *dst = get_dst(ctx, inst);
+ struct tgsi_src_register *a0, *a1;
+ unsigned condition;
- get_internal_temp(ctx, &tmp_dst, &tmp_src);
+ tmp_src = get_internal_temp(ctx, &tmp_dst);
- /* cmps.f.ge tmp, src0, 0.0 */
+ switch (t->tgsi_opc) {
+ case TGSI_OPCODE_SEQ:
+ case TGSI_OPCODE_SNE:
+ a0 = &inst->Src[1].Register; /* b */
+ a1 = &inst->Src[0].Register; /* a */
+ condition = IR3_COND_EQ;
+ break;
+ case TGSI_OPCODE_SGE:
+ case TGSI_OPCODE_SLT:
+ a0 = &inst->Src[0].Register; /* a */
+ a1 = &inst->Src[1].Register; /* b */
+ condition = IR3_COND_GE;
+ break;
+ case TGSI_OPCODE_SLE:
+ case TGSI_OPCODE_SGT:
+ a0 = &inst->Src[1].Register; /* b */
+ a1 = &inst->Src[0].Register; /* a */
+ condition = IR3_COND_GE;
+ break;
+ case TGSI_OPCODE_CMP:
+ get_immediate(ctx, &constval0, fui(0.0));
+ a0 = &inst->Src[0].Register; /* a */
+ a1 = &constval0; /* {0.0} */
+ condition = IR3_COND_GE;
+ break;
+ default:
+ compile_assert(ctx, 0);
+ return;
+ }
+
+ if (is_const(a0) && is_const(a1))
+ a0 = get_unconst(ctx, a0);
+
+ /* cmps.f.ge tmp, a0, a1 */
instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
- instr->cat2.condition = IR3_COND_GE;
- get_immediate(ctx, &constval, fui(0.0));
- vectorize(ctx, instr, &tmp_dst, 2,
- &inst->Src[0].Register, 0,
- &constval, 0);
-
- /* add.s tmp, tmp, -1 */
- instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
- instr->repeat = 3;
- add_dst_reg(ctx, instr, &tmp_dst, 0);
- add_src_reg(ctx, instr, &tmp_src, 0);
- ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
-
- /* sel.{f32,f16} dst, src2, tmp, src1 */
- instr = ir3_instr_create(ctx->ir, 3, ctx->so->half_precision ?
- OPC_SEL_F16 : OPC_SEL_F32);
- vectorize(ctx, instr, &inst->Dst[0].Register, 3,
- &inst->Src[2].Register, 0,
- &tmp_src, 0,
- &inst->Src[1].Register, 0);
+ instr->cat2.condition = condition;
+ vectorize(ctx, instr, &tmp_dst, 2, a0, 0, a1, 0);
+
+ switch (t->tgsi_opc) {
+ case TGSI_OPCODE_SEQ:
+ case TGSI_OPCODE_SGE:
+ case TGSI_OPCODE_SLE:
+ /* cov.u16f16 dst, tmp0 */
+ instr = ir3_instr_create(ctx->ir, 1, 0);
+ instr->cat1.src_type = get_utype(ctx);
+ instr->cat1.dst_type = get_ftype(ctx);
+ vectorize(ctx, instr, dst, 1, tmp_src, 0);
+ break;
+ case TGSI_OPCODE_SNE:
+ case TGSI_OPCODE_SGT:
+ case TGSI_OPCODE_SLT:
+ case TGSI_OPCODE_CMP:
+ /* add.s tmp, tmp, -1 */
+ instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
+ vectorize(ctx, instr, &tmp_dst, 2, tmp_src, 0, -1, IR3_REG_IMMED);
+
+ if (t->tgsi_opc == TGSI_OPCODE_CMP) {
+ /* sel.{f32,f16} dst, src2, tmp, src1 */
+ instr = ir3_instr_create(ctx->ir, 3,
+ ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
+ vectorize(ctx, instr, dst, 3,
+ &inst->Src[2].Register, 0,
+ tmp_src, 0,
+ &inst->Src[1].Register, 0);
+ } else {
+ get_immediate(ctx, &constval0, fui(0.0));
+ get_immediate(ctx, &constval1, fui(1.0));
+ /* sel.{f32,f16} dst, {0.0}, tmp0, {1.0} */
+ instr = ir3_instr_create(ctx->ir, 3,
+ ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
+ vectorize(ctx, instr, dst, 3,
+ &constval0, 0, tmp_src, 0, &constval1, 0);
+ }
+
+ break;
+ }
put_dst(ctx, inst, dst);
}
get_immediate(ctx, &constval, fui(0.0));
+ if (is_const(src))
+ src = get_unconst(ctx, src);
+
instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
ir3_reg_create(instr, regid(REG_P0, 0), 0);
- add_src_reg(ctx, instr, &constval, constval.SwizzleX);
add_src_reg(ctx, instr, src, src->SwizzleX);
+ add_src_reg(ctx, instr, &constval, constval.SwizzleX);
instr->cat2.condition = IR3_COND_EQ;
instr = ir3_instr_create(ctx->ir, 0, OPC_BR);
struct tgsi_full_instruction *inst)
{
struct tgsi_dst_register *dst = get_dst(ctx, inst);
+ struct tgsi_src_register *src0 = &inst->Src[0].Register;
+ struct tgsi_src_register *src1 = &inst->Src[1].Register;
struct ir3_instruction *instr;
+ unsigned src0_flags = 0, src1_flags = 0;
- assert(inst->Instruction.NumSrcRegs == 2);
- assert(inst->Instruction.NumDstRegs == 1);
-
- instr = ir3_instr_create(ctx->ir, 2, t->opc);
- instr->cat2.condition = t->arg;
+ switch (t->tgsi_opc) {
+ case TGSI_OPCODE_ABS:
+ src0_flags = IR3_REG_ABS;
+ break;
+ case TGSI_OPCODE_SUB:
+ src1_flags = IR3_REG_NEGATE;
+ break;
+ }
switch (t->opc) {
case OPC_ABSNEG_F:
case OPC_SETRM:
case OPC_CBITS_B:
/* these only have one src reg */
- vectorize(ctx, instr, dst, 1,
- &inst->Src[0].Register, 0);
+ instr = ir3_instr_create(ctx->ir, 2, t->opc);
+ vectorize(ctx, instr, dst, 1, src0, src0_flags);
break;
default:
- vectorize(ctx, instr, dst, 2,
- &inst->Src[0].Register, 0,
- &inst->Src[1].Register, 0);
+ if (is_const(src0) && is_const(src1))
+ src0 = get_unconst(ctx, src0);
+
+ instr = ir3_instr_create(ctx->ir, 2, t->opc);
+ vectorize(ctx, instr, dst, 2, src0, src0_flags,
+ src1, src1_flags);
break;
}
put_dst(ctx, inst, dst);
}
+static bool is_mad(opc_t opc)
+{
+ switch (opc) {
+ case OPC_MAD_U16:
+ case OPC_MADSH_U16:
+ case OPC_MAD_S16:
+ case OPC_MADSH_M16:
+ case OPC_MAD_U24:
+ case OPC_MAD_S24:
+ case OPC_MAD_F16:
+ case OPC_MAD_F32:
+ return true;
+ default:
+ return false;
+ }
+}
+
static void
instr_cat3(const struct instr_translater *t,
struct fd3_compile_context *ctx,
struct tgsi_full_instruction *inst)
{
struct tgsi_dst_register *dst = get_dst(ctx, inst);
+ struct tgsi_src_register *src0 = &inst->Src[0].Register;
struct tgsi_src_register *src1 = &inst->Src[1].Register;
- struct tgsi_dst_register tmp_dst;
- struct tgsi_src_register tmp_src;
struct ir3_instruction *instr;
- /* Blob compiler never seems to use a const in src1 position..
- * although there does seem (according to disassembler hidden
- * in libllvm-a3xx.so) to be a bit to indicate that src1 is a
- * const. Not sure if this is a hw bug, or simply that the
- * disassembler lies.
+ /* in particular, can't handle const for src1 for cat3..
+ * for mad, we can swap first two src's if needed:
*/
- if ((src1->File == TGSI_FILE_CONSTANT) ||
- (src1->File == TGSI_FILE_IMMEDIATE)) {
- get_internal_temp(ctx, &tmp_dst, &tmp_src);
- create_mov(ctx, &tmp_dst, src1);
- src1 = &tmp_src;
+ if (is_rel_or_const(src1)) {
+ if (is_mad(t->opc) && !is_rel_or_const(src0)) {
+ struct tgsi_src_register *tmp;
+ tmp = src0;
+ src0 = src1;
+ src1 = tmp;
+ } else {
+ src1 = get_unconst(ctx, src1);
+ }
}
instr = ir3_instr_create(ctx->ir, 3,
ctx->so->half_precision ? t->hopc : t->opc);
- vectorize(ctx, instr, dst, 3,
- &inst->Src[0].Register, 0,
- src1, 0,
+ vectorize(ctx, instr, dst, 3, src0, 0, src1, 0,
&inst->Src[2].Register, 0);
put_dst(ctx, inst, dst);
}
struct tgsi_full_instruction *inst)
{
struct tgsi_dst_register *dst = get_dst(ctx, inst);
+ struct tgsi_src_register *src = &inst->Src[0].Register;
struct ir3_instruction *instr;
+ unsigned i, n;
- ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
- instr = ir3_instr_create(ctx->ir, 4, t->opc);
+ /* seems like blob compiler avoids const as src.. */
+ if (is_const(src))
+ src = get_unconst(ctx, src);
- vectorize(ctx, instr, dst, 1,
- &inst->Src[0].Register, 0);
+ /* worst case: */
+ add_nop(ctx, 6);
- regmask_set(ctx->needs_ss, instr->regs[0]);
+ /* we need to replicate into each component: */
+ for (i = 0, n = 0; i < 4; i++) {
+ if (dst->WriteMask & (1 << i)) {
+ if (n++)
+ ir3_instr_create(ctx->ir, 0, OPC_NOP);
+ instr = ir3_instr_create(ctx->ir, 4, t->opc);
+ add_dst_reg(ctx, instr, dst, i);
+ add_src_reg(ctx, instr, src, src->SwizzleX);
+ }
+ }
+ regmask_set(&ctx->needs_ss, instr->regs[0]);
put_dst(ctx, inst, dst);
}
INSTR(SQRT, instr_cat4, .opc = OPC_SQRT),
INSTR(MUL, instr_cat2, .opc = OPC_MUL_F),
INSTR(ADD, instr_cat2, .opc = OPC_ADD_F),
- INSTR(DP2, trans_dotp, .arg = 2),
- INSTR(DP3, trans_dotp, .arg = 3),
- INSTR(DP4, trans_dotp, .arg = 4),
- INSTR(DPH, trans_dotp, .arg = 3), /* almost like DP3 */
+ INSTR(SUB, instr_cat2, .opc = OPC_ADD_F),
INSTR(MIN, instr_cat2, .opc = OPC_MIN_F),
INSTR(MAX, instr_cat2, .opc = OPC_MAX_F),
- INSTR(SLT, instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_LT),
- INSTR(SGE, instr_cat2, .opc = OPC_CMPS_F, .arg = IR3_COND_GE),
INSTR(MAD, instr_cat3, .opc = OPC_MAD_F32, .hopc = OPC_MAD_F16),
- INSTR(LRP, trans_lrp),
- INSTR(FRC, trans_frac),
+ INSTR(TRUNC, instr_cat2, .opc = OPC_TRUNC_F),
+ INSTR(CLAMP, trans_clamp),
INSTR(FLR, instr_cat2, .opc = OPC_FLOOR_F),
+ INSTR(ROUND, instr_cat2, .opc = OPC_RNDNE_F),
+ INSTR(ARL, trans_arl),
INSTR(EX2, instr_cat4, .opc = OPC_EXP2),
INSTR(LG2, instr_cat4, .opc = OPC_LOG2),
- INSTR(POW, trans_pow),
- INSTR(COS, instr_cat4, .opc = OPC_SIN),
- INSTR(SIN, instr_cat4, .opc = OPC_COS),
+ INSTR(ABS, instr_cat2, .opc = OPC_ABSNEG_F),
+ INSTR(COS, instr_cat4, .opc = OPC_COS),
+ INSTR(SIN, instr_cat4, .opc = OPC_SIN),
INSTR(TEX, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TEX),
INSTR(TXP, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TXP),
+ INSTR(SGT, trans_cmp),
+ INSTR(SLT, trans_cmp),
+ INSTR(SGE, trans_cmp),
+ INSTR(SLE, trans_cmp),
+ INSTR(SNE, trans_cmp),
+ INSTR(SEQ, trans_cmp),
INSTR(CMP, trans_cmp),
INSTR(IF, trans_if),
INSTR(ELSE, trans_else),
INSTR(ENDIF, trans_endif),
INSTR(END, instr_cat0, .opc = OPC_END),
+ INSTR(KILL, instr_cat0, .opc = OPC_KILL),
};
-static void
+static fd3_semantic
+decl_semantic(const struct tgsi_declaration_semantic *sem)
+{
+ return fd3_semantic_name(sem->Name, sem->Index);
+}
+
+static int
decl_in(struct fd3_compile_context *ctx, struct tgsi_full_declaration *decl)
{
struct fd3_shader_stateobj *so = ctx->so;
unsigned base = ctx->base_reg[TGSI_FILE_INPUT];
unsigned i, flags = 0;
+ int nop = 0;
+
+ /* I don't think we should get frag shader input without
+ * semantic info? Otherwise how do inputs get linked to
+ * vert outputs?
+ */
+ compile_assert(ctx, (ctx->type == TGSI_PROCESSOR_VERTEX) ||
+ decl->Declaration.Semantic);
if (ctx->so->half_precision)
flags |= IR3_REG_HALF;
DBG("decl in -> r%d", i + base); // XXX
+ so->inputs[n].semantic = decl_semantic(&decl->Semantic);
so->inputs[n].compmask = (1 << ncomp) - 1;
so->inputs[n].regid = r;
so->inputs[n].inloc = ctx->next_inloc;
/* for frag shaders, we need to generate the corresponding bary instr: */
if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
- struct ir3_instruction *instr;
+ unsigned j;
+
+ for (j = 0; j < ncomp; j++) {
+ struct ir3_instruction *instr;
+ struct ir3_register *dst;
- instr = ir3_instr_create(ctx->ir, 2, OPC_BARY_F);
- instr->repeat = ncomp - 1;
+ instr = ir3_instr_create(ctx->ir, 2, OPC_BARY_F);
- /* dst register: */
- ctx->last_input = ir3_reg_create(instr, r, flags);
+ /* dst register: */
+ dst = ir3_reg_create(instr, r + j, flags);
+ ctx->last_input = dst;
- /* input position: */
- ir3_reg_create(instr, 0, IR3_REG_IMMED | IR3_REG_R)->iim_val =
- so->inputs[n].inloc - 8;
+ /* input position: */
+ ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val =
+ so->inputs[n].inloc + j - 8;
- /* input base (always r0.x): */
- ir3_reg_create(instr, regid(0,0), 0);
+ /* input base (always r0.xy): */
+ ir3_reg_create(instr, regid(0,0), 0)->wrmask = 0x3;
+ }
+
+ nop = 6;
}
}
+
+ return nop;
}
static void
{
struct fd3_shader_stateobj *so = ctx->so;
unsigned base = ctx->base_reg[TGSI_FILE_OUTPUT];
+ unsigned comp = 0;
unsigned name = decl->Semantic.Name;
unsigned i;
- assert(decl->Declaration.Semantic); // TODO is this ever not true?
+ compile_assert(ctx, decl->Declaration.Semantic); // TODO is this ever not true?
DBG("decl out[%d] -> r%d", name, decl->Range.First + base); // XXX
if (ctx->type == TGSI_PROCESSOR_VERTEX) {
switch (name) {
case TGSI_SEMANTIC_POSITION:
- so->pos_regid = regid(decl->Range.First + base, 0);
- break;
+ so->writes_pos = true;
+ /* fallthrough */
case TGSI_SEMANTIC_PSIZE:
- so->psize_regid = regid(decl->Range.First + base, 0);
- break;
case TGSI_SEMANTIC_COLOR:
case TGSI_SEMANTIC_GENERIC:
case TGSI_SEMANTIC_FOG:
case TGSI_SEMANTIC_TEXCOORD:
- for (i = decl->Range.First; i <= decl->Range.Last; i++)
- so->outputs[so->outputs_count++].regid = regid(i + base, 0);
break;
default:
- DBG("unknown VS semantic name: %s",
+ compile_error(ctx, "unknown VS semantic name: %s\n",
tgsi_semantic_names[name]);
- assert(0);
}
} else {
switch (name) {
+ case TGSI_SEMANTIC_POSITION:
+ comp = 2; /* tgsi will write to .z component */
+ so->writes_pos = true;
+ /* fallthrough */
case TGSI_SEMANTIC_COLOR:
- so->color_regid = regid(decl->Range.First + base, 0);
break;
default:
- DBG("unknown VS semantic name: %s",
+ compile_error(ctx, "unknown FS semantic name: %s\n",
tgsi_semantic_names[name]);
- assert(0);
}
}
+
+ for (i = decl->Range.First; i <= decl->Range.Last; i++) {
+ unsigned n = so->outputs_count++;
+ so->outputs[n].semantic = decl_semantic(&decl->Semantic);
+ so->outputs[n].regid = regid(i + base, comp);
+ }
}
static void
compile_instructions(struct fd3_compile_context *ctx)
{
struct ir3_shader *ir = ctx->ir;
+ int nop = 0;
while (!tgsi_parse_end_of_tokens(&ctx->parser)) {
tgsi_parse_token(&ctx->parser);
if (decl->Declaration.File == TGSI_FILE_OUTPUT) {
decl_out(ctx, decl);
} else if (decl->Declaration.File == TGSI_FILE_INPUT) {
- decl_in(ctx, decl);
+ nop = decl_in(ctx, decl);
} else if (decl->Declaration.File == TGSI_FILE_SAMPLER) {
decl_samp(ctx, decl);
}
unsigned opc = inst->Instruction.Opcode;
const struct instr_translater *t = &translaters[opc];
+ add_nop(ctx, nop);
+ nop = 0;
+
if (t->fxn) {
t->fxn(t, ctx, inst);
ctx->num_internal_temps = 0;
} else {
- debug_printf("unknown TGSI opc: %s\n",
+ compile_error(ctx, "unknown TGSI opc: %s\n",
tgsi_get_opcode_name(opc));
- tgsi_dump(ctx->tokens, 0);
- assert(0);
+ }
+
+ switch (inst->Instruction.Saturate) {
+ case TGSI_SAT_ZERO_ONE:
+ create_clamp_imm(ctx, &inst->Dst[0].Register,
+ fui(0.0), fui(1.0));
+ break;
+ case TGSI_SAT_MINUS_PLUS_ONE:
+ create_clamp_imm(ctx, &inst->Dst[0].Register,
+ fui(-1.0), fui(1.0));
+ break;
}
break;
if (ctx->last_input)
ctx->last_input->flags |= IR3_REG_EI;
+
+ handle_last_rel(ctx);
}
int
so->ir = ir3_shader_create();
- so->color_regid = regid(63,0);
- so->pos_regid = regid(63,0);
- so->psize_regid = regid(63,0);
+ assert(so->ir);
if (compile_init(&ctx, so, tokens) != TGSI_PARSE_OK)
return -1;
projects / mesa.git / blobdiff