#include "util/u_memory.h"
#include "util/u_helpers.h"
#include "util/u_format.h"
+#include "util/u_viewport.h"
#include "freedreno_resource.h"
#include "freedreno_query_hw.h"
* prsc or dwords: buffer containing constant values
* sizedwords: size of const value buffer
*/
-void
+static void
fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc)
static void
fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
- uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
+ uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
{
+ uint32_t anum = align(num, 4);
uint32_t i;
debug_assert((regid % 4) == 0);
- debug_assert((num % 4) == 0);
- OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
+ OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
- CP_LOAD_STATE_0_NUM_UNIT(num/2));
+ CP_LOAD_STATE_0_NUM_UNIT(anum/2));
OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
for (i = 0; i < num; i++) {
- if (bos[i]) {
+ if (prscs[i]) {
if (write) {
- OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
+ OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
} else {
- OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
+ OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
}
} else {
OUT_RING(ring, 0xbad00000 | (i << 16));
}
}
+
+ for (; i < anum; i++)
+ OUT_RING(ring, 0xffffffff);
}
#define VERT_TEX_OFF 0
[SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
};
struct fd3_context *fd3_ctx = fd3_context(ctx);
- unsigned i, j, off;
- void *ptr;
-
- u_upload_alloc(fd3_ctx->border_color_uploader,
- 0, BORDER_COLOR_UPLOAD_SIZE,
- BORDER_COLOR_UPLOAD_SIZE, &off,
- &fd3_ctx->border_color_buf,
- &ptr);
-
- fd_setup_border_colors(tex, ptr, tex_off[sb]);
+ bool needs_border = false;
+ unsigned i, j;
if (tex->num_samplers > 0) {
/* output sampler state: */
OUT_RING(ring, sampler->texsamp0);
OUT_RING(ring, sampler->texsamp1);
+
+ needs_border |= sampler->needs_border;
}
}
&dummy_view;
struct fd_resource *rsc = fd_resource(view->base.texture);
if (rsc && rsc->base.b.target == PIPE_BUFFER) {
- OUT_RELOC(ring, rsc->bo, view->base.u.buf.first_element *
- util_format_get_blocksize(view->base.format), 0, 0);
+ OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
j = 1;
} else {
unsigned start = fd_sampler_first_level(&view->base);
- unsigned end = fd_sampler_last_level(&view->base);;
+ unsigned end = fd_sampler_last_level(&view->base);
for (j = 0; j < (end - start + 1); j++) {
struct fd_resource_slice *slice =
}
}
- OUT_PKT0(ring, bcolor_reg[sb], 1);
- OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
+ if (needs_border) {
+ unsigned off;
+ void *ptr;
- u_upload_unmap(fd3_ctx->border_color_uploader);
+ u_upload_alloc(fd3_ctx->border_color_uploader,
+ 0, BORDER_COLOR_UPLOAD_SIZE,
+ BORDER_COLOR_UPLOAD_SIZE, &off,
+ &fd3_ctx->border_color_buf,
+ &ptr);
+
+ fd_setup_border_colors(tex, ptr, tex_off[sb]);
+
+ OUT_PKT0(ring, bcolor_reg[sb], 1);
+ OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
+
+ u_upload_unmap(fd3_ctx->border_color_uploader);
+ }
}
/* emit texture state for mem->gmem restore operation.. eventually it would
}
struct fd_resource *rsc = fd_resource(psurf[i]->texture);
- enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
+ enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
/* The restore blit_zs shader expects stencil in sampler 0, and depth
* in sampler 1
*/
if (rsc->stencil && i == 0) {
rsc = rsc->stencil;
- format = fd3_gmem_restore_format(rsc->base.b.format);
+ format = fd_gmem_restore_format(rsc->base.b.format);
}
/* note: PIPE_BUFFER disallowed for surfaces */
OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
- fd3_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
- PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
+ fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
+ PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
int32_t i, j, last = -1;
uint32_t total_in = 0;
const struct fd_vertex_state *vtx = emit->vtx;
- struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
+ const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
unsigned vertex_regid = regid(63, 0);
unsigned instance_regid = regid(63, 0);
unsigned vtxcnt_regid = regid(63, 0);
fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct fd3_emit *emit)
{
- struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
- struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
+ const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
+ const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
uint32_t dirty = emit->dirty;
emit_marker(ring, 5);
*/
OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
- OUT_RINGP(ring, val, &fd3_context(ctx)->rbrc_patches);
+ OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
}
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
}
- if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
+ if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
if (fp->writes_pos) {
val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
if (fp->has_kill) {
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
+ if (!ctx->rasterizer->depth_clip) {
+ val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
+ }
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, val);
}
if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
->gras_cl_clip_cntl;
+ uint8_t planes = ctx->rasterizer->clip_plane_enable;
val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
- /* TODO only use if prog doesn't use clipvertex/clipdist */
- val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
- MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6));
+ if (!emit->key.ucp_enables)
+ val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
+ MIN2(util_bitcount(planes), 6));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, val);
}
- if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
+ if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
uint32_t planes = ctx->rasterizer->clip_plane_enable;
int count = 0;
+ if (emit->key.ucp_enables)
+ planes = 0;
+
while (planes && count < 6) {
int i = ffs(planes) - 1;
planes &= ~(1U << i);
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
OUT_RING(ring, val);
}
- if (dirty & FD_DIRTY_SCISSOR) {
+ if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
+ int minx = scissor->minx;
+ int miny = scissor->miny;
+ int maxx = scissor->maxx;
+ int maxy = scissor->maxy;
+
+ /* Unfortunately there is no separate depth clip disable, only an all
+ * or nothing deal. So when we disable clipping, we must handle the
+ * viewport clip via scissors.
+ */
+ if (!ctx->rasterizer->depth_clip) {
+ struct pipe_viewport_state *vp = &ctx->viewport;
+ minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
+ miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
+ maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
+ maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
+ }
OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
- OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
- OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
-
- ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
- ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
- ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
- ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
+ OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
+ A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
+ OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
+ A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
+
+ ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
+ ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
+ ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
+ ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
}
if (dirty & FD_DIRTY_VIEWPORT) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
}
+ if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
+ float zmin, zmax;
+ int depth = 24;
+ if (ctx->batch->framebuffer.zsbuf) {
+ depth = util_format_get_component_bits(
+ pipe_surface_format(ctx->batch->framebuffer.zsbuf),
+ UTIL_FORMAT_COLORSPACE_ZS, 0);
+ }
+ util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
+ &zmin, &zmax);
+
+ OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
+ if (depth == 32) {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
+ } else if (depth == 16) {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffff));
+ } else {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
+ }
+ }
+
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
int nr_cbufs = pfb->nr_cbufs;
if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
if (!emit->key.binning_pass)
ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
- /* mark clean after emitting consts: */
- ctx->prog.dirty = 0;
}
if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
uint32_t i;
for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
- enum pipe_format format = pipe_surface_format(ctx->framebuffer.cbufs[i]);
+ enum pipe_format format =
+ pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
const struct util_format_description *desc =
util_format_description(format);
bool is_float = util_format_is_float(format);
}
if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
if (dirty & FD_DIRTY_VERTTEX) {
if (vp->has_samp)
- emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
+ emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
else
dirty &= ~FD_DIRTY_VERTTEX;
}
if (dirty & FD_DIRTY_FRAGTEX) {
if (fp->has_samp)
- emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
+ emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
else
dirty &= ~FD_DIRTY_FRAGTEX;
}
* state, there could have been a context switch between ioctls):
*/
void
-fd3_emit_restore(struct fd_context *ctx)
+fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
+ struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
- struct fd_ringbuffer *ring = ctx->ring;
int i;
if (ctx->screen->gpu_id == 320) {
OUT_RING(ring, 0x00000000);
}
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
OUT_RING(ring, 0x00007fff);
OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
- fd3_emit_cache_flush(ctx, ring);
+ fd3_emit_cache_flush(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
OUT_RING(ring, 0x00000000);
- fd_event_write(ctx, ring, CACHE_FLUSH);
+ fd_event_write(batch, ring, CACHE_FLUSH);
if (is_a3xx_p0(ctx->screen)) {
OUT_PKT3(ring, CP_DRAW_INDX, 3);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
- fd_wfi(ctx, ring);
-
- fd_hw_query_enable(ctx, ring);
+ fd_wfi(batch, ring);
- ctx->needs_rb_fbd = true;
+ fd_hw_query_enable(batch, ring);
}
static void
-fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
- struct fd_ringmarker *end)
+fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
{
- __OUT_IB(ring, true, start, end);
+ __OUT_IB(ring, true, target);
}
void
projects / mesa.git / blobdiff