freedreno: constify fd_vsc_pipe

[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 715b437461830092c2da8256cac9619c263fa82a..6509435636c2730c9fcd3d7f9bc8ab44914af8c6 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -314,7 +314,7 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
 
                debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
 
-               OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->tile_mode) |
+               OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
                                 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
                                 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
                                 fd3_tex_swiz(format,  PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
@@ -322,7 +322,7 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
                OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
                                 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
                                 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
-               OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
+               OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->layout.cpp) |
                                 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
                OUT_RING(ring, 0x00000000);
        }
@@ -735,7 +735,6 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        bool is_int = util_format_is_pure_integer(format);
                        bool has_alpha = util_format_has_alpha(format);
                        uint32_t control = blend->rb_mrt[i].control;
-                       uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
 
                        if (is_int) {
                                control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
@@ -746,10 +745,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        if (format == PIPE_FORMAT_NONE)
                                control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
 
-                       if (has_alpha) {
-                               blend_control |= blend->rb_mrt[i].blend_control_rgb;
-                       } else {
-                               blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
+                       if (!has_alpha) {
                                control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
                        }
 
@@ -769,7 +765,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        OUT_RING(ring, control);
 
                        OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
-                       OUT_RING(ring, blend_control |
+                       OUT_RING(ring, blend->rb_mrt[i].blend_control |
                                        COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
                }
        }