-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
/*
* Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
*
#include "util/u_string.h"
#include "util/u_memory.h"
#include "util/u_helpers.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
+#include "util/u_viewport.h"
#include "freedreno_resource.h"
#include "freedreno_query_hw.h"
#include "fd3_zsa.h"
static const enum adreno_state_block sb[] = {
- [SHADER_VERTEX] = SB_VERT_SHADER,
- [SHADER_FRAGMENT] = SB_FRAG_SHADER,
+ [MESA_SHADER_VERTEX] = SB_VERT_SHADER,
+ [MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
};
/* regid: base const register
* prsc or dwords: buffer containing constant values
* sizedwords: size of const value buffer
*/
-void
-fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
+static void
+fd3_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc)
{
}
static void
-fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
+fd3_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
{
+ uint32_t anum = align(num, 4);
uint32_t i;
debug_assert((regid % 4) == 0);
- debug_assert((num % 4) == 0);
- OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
+ OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
- CP_LOAD_STATE_0_NUM_UNIT(num/2));
+ CP_LOAD_STATE_0_NUM_UNIT(anum/2));
OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
OUT_RING(ring, 0xbad00000 | (i << 16));
}
}
+
+ for (; i < anum; i++)
+ OUT_RING(ring, 0xffffffff);
}
#define VERT_TEX_OFF 0
fd3_pipe_sampler_view(tex->textures[i]) :
&dummy_view;
struct fd_resource *rsc = fd_resource(view->base.texture);
- if (rsc && rsc->base.b.target == PIPE_BUFFER) {
- OUT_RELOC(ring, rsc->bo, view->base.u.buf.first_element *
- util_format_get_blocksize(view->base.format), 0, 0);
+ if (rsc && rsc->base.target == PIPE_BUFFER) {
+ OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
j = 1;
} else {
unsigned start = fd_sampler_first_level(&view->base);
unsigned end = fd_sampler_last_level(&view->base);
for (j = 0; j < (end - start + 1); j++) {
- struct fd_resource_slice *slice =
- fd_resource_slice(rsc, j + start);
+ struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
}
}
}
struct fd_resource *rsc = fd_resource(psurf[i]->texture);
- enum pipe_format format = fd3_gmem_restore_format(psurf[i]->format);
+ enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
/* The restore blit_zs shader expects stencil in sampler 0, and depth
* in sampler 1
*/
if (rsc->stencil && i == 0) {
rsc = rsc->stencil;
- format = fd3_gmem_restore_format(rsc->base.b.format);
+ format = fd_gmem_restore_format(rsc->base.format);
}
/* note: PIPE_BUFFER disallowed for surfaces */
unsigned lvl = psurf[i]->u.tex.level;
- struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
+ struct fdl_slice *slice = fd_resource_slice(rsc, lvl);
debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
- OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
+ OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
+ A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
- OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
+ OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->layout.cpp) |
A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
OUT_RING(ring, 0x00000000);
}
continue;
if (vp->inputs[i].sysval) {
switch(vp->inputs[i].slot) {
- case SYSTEM_VALUE_BASE_VERTEX:
- /* handled elsewhere */
- break;
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
vertex_regid = vp->inputs[i].regid;
break;
struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
const struct pipe_vertex_buffer *vb =
&vtx->vertexbuf.vb[elem->vertex_buffer_index];
- struct fd_resource *rsc = fd_resource(vb->buffer);
+ struct fd_resource *rsc = fd_resource(vb->buffer.resource);
enum pipe_format pfmt = elem->src_format;
enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
bool switchnext = (i != last) ||
(instance_regid != regid(63, 0)) ||
(vtxcnt_regid != regid(63, 0));
bool isint = util_format_is_pure_integer(pfmt);
+ uint32_t off = vb->buffer_offset + elem->src_offset;
uint32_t fs = util_format_get_blocksize(pfmt);
+#ifdef DEBUG
+ /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
+ * should mesa/st be protecting us from this?
+ */
+ if (off > fd_bo_size(rsc->bo))
+ continue;
+#endif
+
debug_assert(fmt != ~0);
OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
- OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0);
+ OUT_RELOC(ring, rsc->bo, off, 0, 0);
OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
- total_in += vp->inputs[i].ncomp;
+ total_in += util_bitcount(vp->inputs[i].compmask);
j++;
}
}
{
const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
- uint32_t dirty = emit->dirty;
+ const enum fd_dirty_3d_state dirty = emit->dirty;
emit_marker(ring, 5);
}
if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
- !emit->key.binning_pass) {
+ !emit->binning_pass) {
uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
fd3_blend_stateobj(ctx->blend)->rb_render_control;
A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
}
- if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
+ if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
if (fp->writes_pos) {
val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
- if (fp->has_kill) {
+ if (fp->no_earlyz) {
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
+ if (!ctx->rasterizer->depth_clip_near) {
+ val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
+ }
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, val);
}
if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
->gras_cl_clip_cntl;
+ uint8_t planes = ctx->rasterizer->clip_plane_enable;
val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
- /* TODO only use if prog doesn't use clipvertex/clipdist */
- val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
- MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable), 6));
+ if (!emit->key.ucp_enables)
+ val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
+ MIN2(util_bitcount(planes), 6));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, val);
}
- if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
+ if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
uint32_t planes = ctx->rasterizer->clip_plane_enable;
int count = 0;
+ if (emit->key.ucp_enables)
+ planes = 0;
+
while (planes && count < 6) {
int i = ffs(planes) - 1;
planes &= ~(1U << i);
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
->pc_prim_vtx_cntl;
- if (!emit->key.binning_pass) {
+ if (!emit->binning_pass) {
uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
if (stride_in_vpc > 0)
stride_in_vpc = MAX2(stride_in_vpc, 2);
val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
}
- if (info->indexed && info->primitive_restart) {
+ if (info->index_size && info->primitive_restart) {
val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
}
OUT_RING(ring, val);
}
- if (dirty & FD_DIRTY_SCISSOR) {
+ if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
+ int minx = scissor->minx;
+ int miny = scissor->miny;
+ int maxx = scissor->maxx;
+ int maxy = scissor->maxy;
+
+ /* Unfortunately there is no separate depth clip disable, only an all
+ * or nothing deal. So when we disable clipping, we must handle the
+ * viewport clip via scissors.
+ */
+ if (!ctx->rasterizer->depth_clip_near) {
+ struct pipe_viewport_state *vp = &ctx->viewport;
+ minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
+ miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
+ maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
+ maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
+ }
OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
- OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
- A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
- OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
- A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
-
- ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
- ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
- ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
- ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
+ OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
+ A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
+ OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
+ A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
+
+ ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
+ ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
+ ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
+ ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
}
if (dirty & FD_DIRTY_VIEWPORT) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
}
+ if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
+ float zmin, zmax;
+ int depth = 24;
+ if (ctx->batch->framebuffer.zsbuf) {
+ depth = util_format_get_component_bits(
+ pipe_surface_format(ctx->batch->framebuffer.zsbuf),
+ UTIL_FORMAT_COLORSPACE_ZS, 0);
+ }
+ util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
+ &zmin, &zmax);
+
+ OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
+ if (depth == 32) {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
+ } else if (depth == 16) {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffff));
+ } else {
+ OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
+ OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
+ }
+ }
+
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
int nr_cbufs = pfb->nr_cbufs;
OUT_RING(ring, HLSQ_FLUSH);
if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
- ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
- if (!emit->key.binning_pass)
- ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
+ ir3_emit_vs_consts(vp, ring, ctx, emit->info);
+ if (!emit->binning_pass)
+ ir3_emit_fs_consts(fp, ring, ctx);
}
if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
bool is_int = util_format_is_pure_integer(format);
bool has_alpha = util_format_has_alpha(format);
uint32_t control = blend->rb_mrt[i].control;
- uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
if (is_int) {
control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
if (format == PIPE_FORMAT_NONE)
control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
- if (has_alpha) {
- blend_control |= blend->rb_mrt[i].blend_control_rgb;
- } else {
- blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
+ if (!has_alpha) {
control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
}
OUT_RING(ring, control);
OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
- OUT_RING(ring, blend_control |
+ OUT_RING(ring, blend->rb_mrt[i].blend_control |
COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
}
}
A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
}
- if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX))
- fd_wfi(ctx, ring);
+ if (dirty & FD_DIRTY_TEX)
+ fd_wfi(ctx->batch, ring);
- if (dirty & FD_DIRTY_VERTTEX) {
- if (vp->has_samp)
- emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
- else
- dirty &= ~FD_DIRTY_VERTTEX;
- }
+ if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
+ emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
- if (dirty & FD_DIRTY_FRAGTEX) {
- if (fp->has_samp)
- emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
- else
- dirty &= ~FD_DIRTY_FRAGTEX;
- }
-
- ctx->dirty &= ~dirty;
+ if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
+ emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
}
/* emit setup at begin of new cmdstream buffer (don't rely on previous
OUT_RING(ring, 0x00000000);
}
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
OUT_RING(ring, 0x00007fff);
OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
- fd3_emit_cache_flush(ctx, ring);
+ fd3_emit_cache_flush(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
OUT_RING(ring, 0x00000000);
- fd_event_write(ctx, ring, CACHE_FLUSH);
+ fd_event_write(batch, ring, CACHE_FLUSH);
if (is_a3xx_p0(ctx->screen)) {
OUT_PKT3(ring, CP_DRAW_INDX, 3);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
fd_hw_query_enable(batch, ring);
-
- ctx->needs_rb_fbd = true;
}
-static void
-fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
+void
+fd3_emit_init_screen(struct pipe_screen *pscreen)
{
- __OUT_IB(ring, true, target);
+ struct fd_screen *screen = fd_screen(pscreen);
+ screen->emit_const = fd3_emit_const;
+ screen->emit_const_bo = fd3_emit_const_bo;
+ screen->emit_ib = fd3_emit_ib;
}
void
fd3_emit_init(struct pipe_context *pctx)
{
- struct fd_context *ctx = fd_context(pctx);
- ctx->emit_const = fd3_emit_const;
- ctx->emit_const_bo = fd3_emit_const_bo;
- ctx->emit_ib = fd3_emit_ib;
}