freedreno: constify fd_vsc_pipe

[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.h

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.h b/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
index 668e5ddd095f070020f00ed30a7ae2b21d1f05cd..7a905628dd62d68c40a86ae46143938533bfa85c 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
 /*
  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
  *
@@ -32,58 +30,86 @@
 #include "pipe/p_context.h"
 
 #include "freedreno_context.h"
-#include "fd3_util.h"
-
+#include "fd3_format.h"
+#include "fd3_program.h"
+#include "ir3_gallium.h"
 
 struct fd_ringbuffer;
-enum adreno_state_block;
-
-void fd3_emit_constant(struct fd_ringbuffer *ring,
-               enum adreno_state_block sb,
-               uint32_t regid, uint32_t offset, uint32_t sizedwords,
-               const uint32_t *dwords, struct pipe_resource *prsc);
 
 void fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
-               struct pipe_surface *psurf);
+               struct pipe_surface **psurf, int bufs);
 
-/* NOTE: this just exists because we don't have proper vertex/vertexbuf
- * state objs for clear, and mem2gmem/gmem2mem operations..
- */
-struct fd3_vertex_buf {
-       unsigned offset, stride;
-       struct pipe_resource *prsc;
-       enum pipe_format format;
+/* grouped together emit-state for prog/vertex/state emit: */
+struct fd3_emit {
+       struct pipe_debug_callback *debug;
+       const struct fd_vertex_state *vtx;
+       const struct fd_program_stateobj *prog;
+       const struct pipe_draw_info *info;
+       bool binning_pass;
+       struct ir3_shader_key key;
+       enum fd_dirty_3d_state dirty;
+
+       uint32_t sprite_coord_enable;
+       bool sprite_coord_mode;
+       bool rasterflat;
+
+       /* cached to avoid repeated lookups of same variants: */
+       const struct ir3_shader_variant *vs, *fs;
 };
 
-void fd3_emit_vertex_bufs(struct fd_ringbuffer *ring,
-               struct fd_program_stateobj *prog,
-               struct fd3_vertex_buf *vbufs, uint32_t n);
-void fd3_emit_state(struct fd_context *ctx, uint32_t dirty);
-void fd3_emit_restore(struct fd_context *ctx);
+static inline const struct ir3_shader_variant *
+fd3_emit_get_vp(struct fd3_emit *emit)
+{
+       if (!emit->vs) {
+               struct ir3_shader *shader = emit->prog->vs;
+               emit->vs = ir3_shader_variant(shader, emit->key,
+                               emit->binning_pass, emit->debug);
+       }
+       return emit->vs;
+}
 
+static inline const struct ir3_shader_variant *
+fd3_emit_get_fp(struct fd3_emit *emit)
+{
+       if (!emit->fs) {
+               if (emit->binning_pass) {
+                       /* use dummy stateobj to simplify binning vs non-binning: */
+                       static const struct ir3_shader_variant binning_fs = {};
+                       emit->fs = &binning_fs;
+               } else {
+                       struct ir3_shader *shader = emit->prog->fs;
+                       emit->fs = ir3_shader_variant(shader, emit->key,
+                                       false, emit->debug);
+               }
+       }
+       return emit->fs;
+}
+
+void fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit);
+
+void fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
+               struct fd3_emit *emit);
+
+void fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
+
+void fd3_emit_init_screen(struct pipe_screen *pscreen);
+void fd3_emit_init(struct pipe_context *pctx);
 
-/* use RMW (read-modify-write) to update RB_RENDER_CONTROL since the
- * GMEM/binning code is deciding on the bin-width (and whether to
- * use binning) after the draw/clear state is emitted.
- */
 static inline void
-fd3_emit_rbrc_draw_state(struct fd_ringbuffer *ring, uint32_t val)
+fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 {
-       OUT_PKT3(ring, CP_REG_RMW, 3);
-       OUT_RING(ring, REG_A3XX_RB_RENDER_CONTROL);
-       OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK |
-                       A3XX_RB_RENDER_CONTROL_ENABLE_GMEM);
-       OUT_RING(ring, val);
+       __OUT_IB(ring, true, target);
 }
 
 static inline void
-fd3_emit_rbrc_tile_state(struct fd_ringbuffer *ring, uint32_t val)
+fd3_emit_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
 {
-       OUT_PKT3(ring, CP_REG_RMW, 3);
-       OUT_RING(ring, REG_A3XX_RB_RENDER_CONTROL);
-       OUT_RING(ring, ~(A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK |
-                       A3XX_RB_RENDER_CONTROL_ENABLE_GMEM));
-       OUT_RING(ring, val);
+       fd_wfi(batch, ring);
+       OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
+       OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
+       OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
+                       A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
+                       A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
 }
 
 #endif /* FD3_EMIT_H */