freedreno/a3xx+a4xx: fix for stk binning pass hang

[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index a6824ef92e7719b04f2d9ea90481c80778d187c9..4ed04b38dea72efcc7cb65893e8755cb991b6574 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -51,7 +51,7 @@ create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state
                enum shader_t type)
 {
        struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
-       so->shader = ir3_shader_create(pctx, cso->tokens, type);
+       so->shader = ir3_shader_create(pctx, cso, type);
        return so;
 }
 
@@ -136,6 +136,8 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
        int constmode;
        int i, j, k;
 
+       debug_assert(nr <= ARRAY_SIZE(color_regid));
+
        vp = fd3_emit_get_vp(emit);
 
        if (emit->key.binning_pass) {
@@ -192,24 +194,17 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
        /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
        constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
 
-       pos_regid = ir3_find_output_regid(vp,
-               ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
-       posz_regid = ir3_find_output_regid(fp,
-               ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
-       psize_regid = ir3_find_output_regid(vp,
-               ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
+       pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
+       posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
+       psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
        if (fp->color0_mrt) {
                color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
-                       ir3_find_output_regid(fp, ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
+                       ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
        } else {
-               for (int i = 0; i < fp->outputs_count; i++) {
-                       ir3_semantic sem = fp->outputs[i].semantic;
-                       unsigned idx = sem2idx(sem);
-                       if (sem2name(sem) != TGSI_SEMANTIC_COLOR)
-                               continue;
-                       assert(idx < 4);
-                       color_regid[idx] = fp->outputs[i].regid;
-               }
+               color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
+               color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
+               color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
+               color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
        }
 
        /* adjust regids for alpha output formats. there is no alpha render
@@ -278,14 +273,14 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 
                j = ir3_next_varying(fp, j);
                if (j < fp->inputs_count) {
-                       k = ir3_find_output(vp, fp->inputs[j].semantic);
+                       k = ir3_find_output(vp, fp->inputs[j].slot);
                        reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
                        reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
                }
 
                j = ir3_next_varying(fp, j);
                if (j < fp->inputs_count) {
-                       k = ir3_find_output(vp, fp->inputs[j].semantic);
+                       k = ir3_find_output(vp, fp->inputs[j].slot);
                        reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
                        reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
                }
@@ -392,7 +387,6 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 
                /* figure out VARYING_INTERP / FLAT_SHAD register values: */
                for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
-                       uint32_t interp = fp->inputs[j].interpolate;
 
                        /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
                         * instead.. rather than -8 everywhere else..
@@ -404,8 +398,8 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
                         */
                        debug_assert((inloc % 4) == 0);
 
-                       if ((interp == TGSI_INTERPOLATE_CONSTANT) ||
-                                       ((interp == TGSI_INTERPOLATE_COLOR) && emit->rasterflat)) {
+                       if ((fp->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
+                                       (fp->inputs[j].rasterflat && emit->rasterflat)) {
                                uint32_t loc = inloc;
                                for (i = 0; i < 4; i++, loc++) {
                                        vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
@@ -413,12 +407,21 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
                                }
                        }
 
-                       /* TODO: Figure out if there's a way to make it spit out 0's and
-                        * 1's for the .z and .w components.
-                        */
-                       if (emit->sprite_coord_enable & (1 << sem2idx(fp->inputs[j].semantic)))
-                               vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
-                                       << ((inloc % 16) * 2);
+                       gl_varying_slot slot = fp->inputs[j].slot;
+
+                       /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
+                       if (slot >= VARYING_SLOT_VAR0) {
+                               unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
+                               /* Replace the .xy coordinates with S/T from the point sprite. Set
+                                * interpolation bits for .zw such that they become .01
+                                */
+                               if (emit->sprite_coord_enable & texmask) {
+                                       vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
+                                                       << ((inloc % 16) * 2);
+                                       vinterp[(inloc + 2) / 16] |= 2 << (((inloc + 2) % 16) * 2);
+                                       vinterp[(inloc + 3) / 16] |= 3 << (((inloc + 3) % 16) * 2);
+                               }
+                       }
                }
 
                OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
@@ -446,10 +449,6 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
                OUT_RING(ring, flatshade[1]);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
        }
 
-       OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
-       OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
-                       A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
-
        if (vpbuffer == BUFFER)
                emit_shader(ring, vp);