freedreno/ir3: bit of shader API refactoring

[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index 1250dffe29e929830859163422cc2e48d99b0a34..9bf42f5b9310f9aceb81d9fbd846a9f7f930835f 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -31,8 +31,6 @@
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
 #include "util/u_format.h"
-#include "tgsi/tgsi_dump.h"
-#include "tgsi/tgsi_parse.h"
 
 #include "freedreno_program.h"
 
@@ -53,7 +51,7 @@ create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state
                enum shader_t type)
 {
        struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
-       so->shader = ir3_shader_create(pctx, cso->tokens, type);
+       so->shader = ir3_shader_create(pctx, cso, type);
        return so;
 }
 
@@ -127,13 +125,14 @@ emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
 }
 
 void
-fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
+fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
+                                int nr, struct pipe_surface **bufs)
 {
        const struct ir3_shader_variant *vp, *fp;
        const struct ir3_info *vsi, *fsi;
        enum a3xx_instrbuffermode fpbuffer, vpbuffer;
        uint32_t fpbuffersz, vpbuffersz, fsoff;
-       uint32_t pos_regid, posz_regid, psize_regid, color_regid;
+       uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
        int constmode;
        int i, j, k;
 
@@ -199,8 +198,26 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
                ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
        psize_regid = ir3_find_output_regid(vp,
                ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
-       color_regid = ir3_find_output_regid(fp,
-               ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
+       if (fp->color0_mrt) {
+               color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
+                       ir3_find_output_regid(fp, ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
+       } else {
+               for (int i = 0; i < fp->outputs_count; i++) {
+                       ir3_semantic sem = fp->outputs[i].semantic;
+                       unsigned idx = sem2idx(sem);
+                       if (sem2name(sem) != TGSI_SEMANTIC_COLOR)
+                               continue;
+                       assert(idx < 4);
+                       color_regid[idx] = fp->outputs[i].regid;
+               }
+       }
+
+       /* adjust regids for alpha output formats. there is no alpha render
+        * format, so it's just treated like red
+        */
+       for (i = 0; i < nr; i++)
+               if (util_format_is_alpha(pipe_surface_format(bufs[i])))
+                       color_regid[i] += 3;
 
        /* we could probably divide this up into things that need to be
         * emitted if frag-prog is dirty vs if vert-prog is dirty..
@@ -342,21 +359,23 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
        }
 
        OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
-       if (fp->writes_pos) {
-               OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE |
-                               A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
-       } else {
-               OUT_RING(ring, 0x00000000);
-       }
+       OUT_RING(ring,
+                        COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
+                        A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
+                        A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
 
        OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
-       OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(color_regid) |
-                       COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION) |
-                       COND(util_format_is_pure_uint(emit->format), A3XX_SP_FS_MRT_REG_UINT) |
-                       COND(util_format_is_pure_sint(emit->format), A3XX_SP_FS_MRT_REG_SINT));
-       OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
-       OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
-       OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
+       for (i = 0; i < 4; i++) {
+               uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
+                       COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
+
+               if (i < nr) {
+                       enum pipe_format fmt = pipe_surface_format(bufs[i]);
+                       mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
+                               COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
+               }
+               OUT_RING(ring, mrt_reg);
+       }
 
        if (emit->key.binning_pass) {
                OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
@@ -394,11 +413,15 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
                                }
                        }
 
-                       /* TODO: Figure out if there's a way to make it spit out 0's and
-                        * 1's for the .z and .w components.
+                       /* Replace the .xy coordinates with S/T from the point sprite. Set
+                        * interpolation bits for .zw such that they become .01
                         */
-                       if (emit->sprite_coord_enable & (1 << sem2idx(fp->inputs[j].semantic)))
-                               vpsrepl[inloc / 16] |= 0x09 << ((inloc % 16) * 2);
+                       if (emit->sprite_coord_enable & (1 << sem2idx(fp->inputs[j].semantic))) {
+                               vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
+                                       << ((inloc % 16) * 2);
+                               vinterp[(inloc + 2) / 16] |= 2 << (((inloc + 2) % 16) * 2);
+                               vinterp[(inloc + 3) / 16] |= 3 << (((inloc + 3) % 16) * 2);
+                       }
                }
 
                OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);