#include "tgsi/tgsi_dump.h"
#include "tgsi/tgsi_parse.h"
+#include "freedreno_lowering.h"
+
#include "fd3_program.h"
#include "fd3_compiler.h"
+#include "fd3_emit.h"
#include "fd3_texture.h"
#include "fd3_util.h"
bin = ir3_shader_assemble(so->ir, &so->info);
sz = so->info.sizedwords * 4;
- so->bo = fd_bo_new(ctx->screen->dev, sz,
+ so->bo = fd_bo_new(ctx->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM);
fixup_vp_regfootprint(struct fd3_shader_stateobj *so)
{
unsigned i;
- for (i = 0; i < so->inputs_count; i++) {
+ for (i = 0; i < so->inputs_count; i++)
so->info.max_reg = MAX2(so->info.max_reg, so->inputs[i].regid >> 2);
- }
+ for (i = 0; i < so->outputs_count; i++)
+ so->info.max_reg = MAX2(so->info.max_reg, so->outputs[i].regid >> 2);
}
static struct fd3_shader_stateobj *
enum shader_t type)
{
struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
+ const struct tgsi_token *tokens = fd_transform_lowering(cso->tokens);
int ret;
if (!so)
if (fd_mesa_debug & FD_DBG_DISASM) {
DBG("dump tgsi: type=%d", so->type);
- tgsi_dump(cso->tokens, 0);
+ tgsi_dump(tokens, 0);
}
- if (type == SHADER_FRAGMENT) {
- /* we seem to get wrong colors (maybe swap/endianess or hw issue?)
- * with full precision color reg. And blob driver only seems to
- * use half precision register for color output (that I can find
- * so far), even with highp precision. So for force half precision
- * for frag shader:
- */
+ if ((type == SHADER_FRAGMENT) && (fd_mesa_debug & FD_DBG_FRAGHALF))
so->half_precision = true;
- }
- ret = fd3_compile_shader(so, cso->tokens);
+ ret = fd3_compile_shader(so, tokens);
if (ret) {
debug_error("compile failed!");
goto fail;
}
static void
-emit_shader(struct fd_ringbuffer *ring, struct fd3_shader_stateobj *so)
+emit_shader(struct fd_ringbuffer *ring, const struct fd3_shader_stateobj *so)
{
- struct ir3_shader_info *si = &so->info;
+ const struct ir3_shader_info *si = &so->info;
enum adreno_state_block sb;
- uint32_t i, *bin;
+ enum adreno_state_src src;
+ uint32_t i, sz, *bin;
if (so->type == SHADER_VERTEX) {
sb = SB_VERT_SHADER;
sb = SB_FRAG_SHADER;
}
- // XXX use SS_INDIRECT
- bin = fd_bo_map(so->bo);
- OUT_PKT3(ring, CP_LOAD_STATE, 2 + si->sizedwords);
+ if (fd_mesa_debug & FD_DBG_DIRECT) {
+ sz = si->sizedwords;
+ src = SS_DIRECT;
+ bin = fd_bo_map(so->bo);
+ } else {
+ sz = 0;
+ src = SS_INDIRECT;
+ bin = NULL;
+ }
+
+ OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
- CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
+ CP_LOAD_STATE_0_STATE_SRC(src) |
CP_LOAD_STATE_0_STATE_BLOCK(sb) |
CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
- OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
- CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
- for (i = 0; i < si->sizedwords; i++)
+ if (bin) {
+ OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
+ CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
+ } else {
+ OUT_RELOC(ring, so->bo, 0,
+ CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
+ }
+ for (i = 0; i < sz; i++) {
OUT_RING(ring, bin[i]);
+ }
+}
+
+static int
+find_output(const struct fd3_shader_stateobj *so, fd3_semantic semantic)
+{
+ int j;
+ for (j = 0; j < so->outputs_count; j++)
+ if (so->outputs[j].semantic == semantic)
+ return j;
+ return 0;
+}
+
+static uint32_t
+find_output_regid(const struct fd3_shader_stateobj *so, fd3_semantic semantic)
+{
+ int j;
+ for (j = 0; j < so->outputs_count; j++)
+ if (so->outputs[j].semantic == semantic)
+ return so->outputs[j].regid;
+ return regid(63, 0);
}
void
fd3_program_emit(struct fd_ringbuffer *ring,
- struct fd_program_stateobj *prog)
+ struct fd_program_stateobj *prog, bool binning)
{
- struct fd3_shader_stateobj *vp = prog->vp;
- struct fd3_shader_stateobj *fp = prog->fp;
- struct ir3_shader_info *vsi = &vp->info;
- struct ir3_shader_info *fsi = &fp->info;
+ const struct fd3_shader_stateobj *vp = prog->vp;
+ const struct fd3_shader_stateobj *fp = prog->fp;
+ const struct ir3_shader_info *vsi = &vp->info;
+ const struct ir3_shader_info *fsi = &fp->info;
+ uint32_t pos_regid, posz_regid, psize_regid, color_regid;
int i;
+ if (binning) {
+ /* use dummy stateobj to simplify binning vs non-binning: */
+ static const struct fd3_shader_stateobj binning_fp = {};
+ fp = &binning_fp;
+ fsi = &fp->info;
+ }
+
+ pos_regid = find_output_regid(vp,
+ fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
+ posz_regid = find_output_regid(fp,
+ fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
+ psize_regid = find_output_regid(vp,
+ fd3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
+ color_regid = find_output_regid(fp,
+ fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
+
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
*/
OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
+ /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
+ * flush some caches? I think we only need to set those
+ * bits if we have updated const or shader..
+ */
A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(0) |
+ COND(binning, A3XX_SP_SP_CTRL_REG_BINNING) |
A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
- // XXX "resolve" (?) bit set on gmem->mem pass..
-// COND(!uniforms, A3XX_SP_SP_CTRL_REG_RESOLVE) |
- // XXX sometimes 0, sometimes 1:
- A3XX_SP_SP_CTRL_REG_LOMODE(1));
-
- /* emit unknown sequence of perfcounter disables that the blob
- * emits as part of the program state..
- */
- for (i = 0; i < 6; i++) {
- OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER0_SELECT, 1);
- OUT_RING(ring, 0x00000000); /* SP_PERFCOUNTER0_SELECT */
-
- OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER4_SELECT, 1);
- OUT_RING(ring, 0x00000000); /* SP_PERFCOUNTER4_SELECT */
- }
+ A3XX_SP_SP_CTRL_REG_L0MODE(0));
OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
+ A3XX_SP_VS_CTRL_REG0_CACHEINVALID |
A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vsi->max_const, 0)));
- OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(vp->pos_regid) |
- A3XX_SP_VS_PARAM_REG_PSIZEREGID(vp->psize_regid) |
- A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(vp->outputs_count));
-
- assert(vp->outputs_count >= fp->inputs_count);
+ OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
+ A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
+ A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->inputs_count));
for (i = 0; i < fp->inputs_count; ) {
uint32_t reg = 0;
+ int j;
OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i/2), 1);
- reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[i].regid);
+ j = find_output(vp, fp->inputs[i].semantic);
+ reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[j].regid);
reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[i].compmask);
i++;
- reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[i].regid);
+ j = find_output(vp, fp->inputs[i].semantic);
+ reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[j].regid);
reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[i].compmask);
i++;
OUT_RING(ring, reg);
}
-#if 0
- /* for some reason, when I write SP_{VS,FS}_OBJ_START_REG I get:
-[ 666.663665] kgsl kgsl-3d0: |a3xx_err_callback| RBBM | AHB bus error | READ | addr=201 | ports=1:3
-[ 666.664001] kgsl kgsl-3d0: |a3xx_err_callback| ringbuffer AHB error interrupt
-[ 670.680909] kgsl kgsl-3d0: |adreno_idle| spun too long waiting for RB to idle
-[ 670.681062] kgsl kgsl-3d0: |kgsl-3d0| Dump Started
-[ 670.681123] kgsl kgsl-3d0: POWER: FLAGS = 00000007 | ACTIVE POWERLEVEL = 00000001
-[ 670.681214] kgsl kgsl-3d0: POWER: INTERVAL TIMEOUT = 0000000A
-[ 670.681367] kgsl kgsl-3d0: GRP_CLK = 325000000
-[ 670.681489] kgsl kgsl-3d0: BUS CLK = 0
- */
OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
-#endif
-
- OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
- OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
-
- OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
- OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
- A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
- A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
- A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
- A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
- A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
- A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
- COND(fp->samplers_count > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
- A3XX_SP_FS_CTRL_REG0_LENGTH(fp->instrlen));
- OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
- A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
- A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fsi->max_const, 0)) |
- A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
-
-#if 0
- OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
- OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
- A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(128 - fp->instrlen));
- OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
-#endif
+
+ if (binning) {
+ OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
+ OUT_RING(ring, 0x00000000);
+
+ OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
+ OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
+ A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
+ OUT_RING(ring, 0x00000000);
+ } else {
+ OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
+ OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
+
+ OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
+ OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
+ A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
+ A3XX_SP_FS_CTRL_REG0_CACHEINVALID |
+ A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
+ A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
+ A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
+ A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
+ A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
+ COND(fp->samplers_count > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
+ A3XX_SP_FS_CTRL_REG0_LENGTH(fp->instrlen));
+ OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
+ A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
+ A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fsi->max_const, 0)) |
+ A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
+ OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
+ OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
+ A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
+ OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
+ }
OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
- OUT_RING(ring, 0x00000000); /* SP_FS_OUTPUT_REG */
+ if (fp->writes_pos) {
+ OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE |
+ A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
+ } else {
+ OUT_RING(ring, 0x00000000);
+ }
OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
- OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(fp->color_regid) |
+ OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(color_regid) |
COND(fp->half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION));
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
- OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
- OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
- A3XX_VPC_ATTR_THRDASSIGN(1) |
- A3XX_VPC_ATTR_LMSIZE(1));
- OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
- A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
-
- OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
- OUT_RING(ring, fp->vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
- OUT_RING(ring, fp->vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
- OUT_RING(ring, fp->vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
- OUT_RING(ring, fp->vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
-
- OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
- OUT_RING(ring, fp->vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
- OUT_RING(ring, fp->vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
- OUT_RING(ring, fp->vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
- OUT_RING(ring, fp->vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
+ if (binning) {
+ OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
+ OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
+ A3XX_VPC_ATTR_LMSIZE(1));
+ OUT_RING(ring, 0x00000000);
+ } else {
+ OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
+ OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
+ A3XX_VPC_ATTR_THRDASSIGN(1) |
+ A3XX_VPC_ATTR_LMSIZE(1));
+ OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
+ A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
+
+ OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
+ OUT_RING(ring, fp->vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
+ OUT_RING(ring, fp->vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
+ OUT_RING(ring, fp->vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
+ OUT_RING(ring, fp->vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
+
+ OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
+ OUT_RING(ring, fp->vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
+ OUT_RING(ring, fp->vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
+ OUT_RING(ring, fp->vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
+ OUT_RING(ring, fp->vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
+ }
OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
- emit_shader(ring, fp);
+ if (!binning) {
+ emit_shader(ring, fp);
- OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
- OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
+ OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
+ OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
+ }
OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(vp->total_in) |
{
struct fd3_shader_stateobj *so;
struct ir3_shader *ir = ir3_shader_create();
+ struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
struct ir3_instruction *instr;
/* (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x */
- instr = ir3_instr_create(ir, 2, OPC_BARY_F);
+ instr = ir3_instr_create(block, 2, OPC_BARY_F);
instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
instr->repeat = 1;
ir3_reg_create(instr, regid(0,0), 0); /* r0.x */
/* (rpt5)nop */
- instr = ir3_instr_create(ir, 0, OPC_NOP);
+ instr = ir3_instr_create(block, 0, OPC_NOP);
instr->repeat = 5;
/* sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 */
- instr = ir3_instr_create(ir, 5, OPC_SAM);
+ instr = ir3_instr_create(block, 5, OPC_SAM);
instr->cat5.samp = 0;
instr->cat5.tex = 0;
instr->cat5.type = TYPE_F32;
ir3_reg_create(instr, regid(0,2), 0); /* r0.z */
/* (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x */
- instr = ir3_instr_create(ir, 1, 0); /* mov/cov instructions have no opc */
+ instr = ir3_instr_create(block, 1, 0); /* mov/cov instructions have no opc */
instr->flags = IR3_INSTR_SY;
instr->repeat = 3;
instr->cat1.src_type = TYPE_F32;
ir3_reg_create(instr, regid(0,0), IR3_REG_R); /* (r)r0.x */
/* end */
- instr = ir3_instr_create(ir, 0, OPC_END);
+ instr = ir3_instr_create(block, 0, OPC_END);
so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
if (!so)
return NULL;
- so->color_regid = regid(0,0);
so->half_precision = true;
so->inputs_count = 1;
+ so->inputs[0].semantic =
+ fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
so->inputs[0].inloc = 8;
so->inputs[0].compmask = 0x3;
so->total_in = 2;
+ so->outputs_count = 1;
+ so->outputs[0].semantic =
+ fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0);
+ so->outputs[0].regid = regid(0,0);
so->samplers_count = 1;
so->vpsrepl[0] = 0x99999999;
{
struct fd3_shader_stateobj *so;
struct ir3_shader *ir = ir3_shader_create();
+ struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
struct ir3_instruction *instr;
/* (sy)(ss)end */
- instr = ir3_instr_create(ir, 0, OPC_END);
+ instr = ir3_instr_create(block, 0, OPC_END);
instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
so = create_internal_shader(pctx, SHADER_VERTEX, ir);
if (!so)
return NULL;
- so->pos_regid = regid(1,0);
- so->psize_regid = regid(63,0);
so->inputs_count = 2;
so->inputs[0].regid = regid(0,0);
so->inputs[0].compmask = 0xf;
so->inputs[1].regid = regid(1,0);
so->inputs[1].compmask = 0xf;
so->total_in = 8;
- so->outputs_count = 1;
+ so->outputs_count = 2;
+ so->outputs[0].semantic =
+ fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
so->outputs[0].regid = regid(0,0);
+ so->outputs[1].semantic =
+ fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0);
+ so->outputs[1].regid = regid(1,0);
fixup_vp_regfootprint(so);
{
struct fd3_shader_stateobj *so;
struct ir3_shader *ir = ir3_shader_create();
+ struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
struct ir3_instruction *instr;
/* (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x */
- instr = ir3_instr_create(ir, 1, 0); /* mov/cov instructions have no opc */
+ instr = ir3_instr_create(block, 1, 0); /* mov/cov instructions have no opc */
instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
instr->repeat = 3;
instr->cat1.src_type = TYPE_F16;
IR3_REG_CONST | IR3_REG_R);
/* end */
- instr = ir3_instr_create(ir, 0, OPC_END);
+ instr = ir3_instr_create(block, 0, OPC_END);
so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
if (!so)
return NULL;
- so->color_regid = regid(0,0);
so->half_precision = true;
so->inputs_count = 0;
+ so->outputs_count = 1;
+ so->outputs[0].semantic =
+ fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0);
+ so->outputs[0].regid = regid(0, 0);
so->total_in = 0;
return so;
{
struct fd3_shader_stateobj *so;
struct ir3_shader *ir = ir3_shader_create();
+ struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
struct ir3_instruction *instr;
/* (sy)(ss)end */
- instr = ir3_instr_create(ir, 0, OPC_END);
+ instr = ir3_instr_create(block, 0, OPC_END);
instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
if (!so)
return NULL;
- so->pos_regid = regid(0,0);
- so->psize_regid = regid(63,0);
so->inputs_count = 1;
so->inputs[0].regid = regid(0,0);
so->inputs[0].compmask = 0xf;
so->total_in = 4;
- so->outputs_count = 0;
+
+ so->outputs_count = 1;
+ so->outputs[0].semantic =
+ fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0);
+ so->outputs[0].regid = regid(0,0);
fixup_vp_regfootprint(so);
projects / mesa.git / blobdiff