freedreno: update generated headers

[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_draw.h

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.h b/src/gallium/drivers/freedreno/a4xx/fd4_draw.h
index 2b23e33b42fe0f7ae0c8938f1d62985fa6dbbe21..f7a7d92453b27c014d90cc9d90d8e99276cabe95 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.h
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.h
@@ -48,13 +48,13 @@ static inline uint32_t DRAW4(enum pc_di_primtype prim_type,
 }
 
 static inline void
-fd4_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
+fd4_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
                enum pc_di_primtype primtype,
                enum pc_di_vis_cull_mode vismode,
                enum pc_di_src_sel src_sel, uint32_t count,
                uint32_t instances, enum a4xx_index_size idx_type,
                uint32_t idx_size, uint32_t idx_offset,
-               struct fd_bo *idx_bo)
+               struct pipe_resource *idx_buffer)
 {
        /* for debug after a lock up, write a unique counter value
         * to scratch7 for each draw, to make it easier to match up
@@ -64,31 +64,30 @@ fd4_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
         */
        emit_marker(ring, 7);
 
-       OUT_PKT3(ring, CP_DRAW_INDX_OFFSET, idx_bo ? 6 : 3);
+       OUT_PKT3(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 6 : 3);
        if (vismode == USE_VISIBILITY) {
                /* leave vis mode blank for now, it will be patched up when
                 * we know if we are binning or not
                 */
                OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0),
-                               &ctx->draw_patches);
+                               &batch->draw_patches);
        } else {
                OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode));
        }
        OUT_RING(ring, instances);         /* NumInstances */
        OUT_RING(ring, count);             /* NumIndices */
-       if (idx_bo) {
+       if (idx_buffer) {
                OUT_RING(ring, 0x0);           /* XXX */
-               OUT_RELOC(ring, idx_bo, idx_offset, 0, 0);
+               OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
                OUT_RING (ring, idx_size);
        }
 
        emit_marker(ring, 7);
 
-       fd_reset_wfi(ctx);
+       fd_reset_wfi(batch);
 }
 
-
-static inline enum pc_di_index_size
+static inline enum a4xx_index_size
 fd4_size2indextype(unsigned index_size)
 {
        switch (index_size) {
@@ -100,37 +99,67 @@ fd4_size2indextype(unsigned index_size)
        assert(0);
        return INDEX4_SIZE_32_BIT;
 }
+
 static inline void
-fd4_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
+fd4_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
                enum pc_di_primtype primtype,
                enum pc_di_vis_cull_mode vismode,
-               const struct pipe_draw_info *info)
+               const struct pipe_draw_info *info,
+               unsigned index_offset)
 {
-       struct pipe_index_buffer *idx = &ctx->indexbuf;
-       struct fd_bo *idx_bo = NULL;
+       struct pipe_resource *idx_buffer = NULL;
        enum a4xx_index_size idx_type;
        enum pc_di_src_sel src_sel;
        uint32_t idx_size, idx_offset;
 
-       if (info->indexed) {
-               assert(!idx->user_buffer);
+       if (info->indirect) {
+               struct fd_resource *ind = fd_resource(info->indirect->buffer);
+
+               emit_marker(ring, 7);
+
+               if (info->index_size) {
+                       struct pipe_resource *idx = info->index.resource;
+
+                       OUT_PKT3(ring, CP_DRAW_INDX_INDIRECT, 4);
+                       OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
+                                       fd4_size2indextype(info->index_size), 0),
+                                       &batch->draw_patches);
+                       OUT_RELOC(ring, fd_resource(idx)->bo, index_offset, 0, 0);
+                       OUT_RING(ring, A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(
+                                                        idx->width0 - index_offset));
+                       OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
+               } else {
+                       OUT_PKT3(ring, CP_DRAW_INDIRECT, 2);
+                       OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
+                                       &batch->draw_patches);
+                       OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
+               }
+
+               emit_marker(ring, 7);
+               fd_reset_wfi(batch);
+
+               return;
+       }
+
+       if (info->index_size) {
+               assert(!info->has_user_indices);
 
-               idx_bo = fd_resource(idx->buffer)->bo;
-               idx_type = fd4_size2indextype(idx->index_size);
-               idx_size = idx->index_size * info->count;
-               idx_offset = idx->offset + (info->start * idx->index_size);
+               idx_buffer = info->index.resource;
+               idx_type = fd4_size2indextype(info->index_size);
+               idx_size = info->index_size * info->count;
+               idx_offset = index_offset + info->start * info->index_size;
                src_sel = DI_SRC_SEL_DMA;
        } else {
-               idx_bo = NULL;
+               idx_buffer = NULL;
                idx_type = INDEX4_SIZE_32_BIT;
                idx_size = 0;
                idx_offset = 0;
                src_sel = DI_SRC_SEL_AUTO_INDEX;
        }
 
-       fd4_draw(ctx, ring, primtype, vismode, src_sel,
+       fd4_draw(batch, ring, primtype, vismode, src_sel,
                        info->count, info->instance_count,
-                       idx_type, idx_size, idx_offset, idx_bo);
+                       idx_type, idx_size, idx_offset, idx_buffer);
 }
 
 #endif /* FD4_DRAW_H_ */