-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
/*
* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
*
#include "util/u_string.h"
#include "util/u_memory.h"
#include "util/u_helpers.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "util/u_viewport.h"
#include "freedreno_resource.h"
#include "fd4_format.h"
#include "fd4_zsa.h"
+#include "ir3_const.h"
+
/* regid: base const register
* prsc or dwords: buffer containing constant values
* sizedwords: size of const value buffer
*/
static void
-fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
+fd4_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc)
{
}
static void
-fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
+fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
{
uint32_t anum = align(num, 4);
for (i = 0; i < num; i++) {
if (prscs[i]) {
- if (write) {
- OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
- } else {
- OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
- }
+ OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
} else {
OUT_RING(ring, 0xbad00000 | (i << 16));
}
OUT_RING(ring, 0xffffffff);
}
+static bool
+is_stateobj(struct fd_ringbuffer *ring)
+{
+ return false;
+}
+
+void
+emit_const(struct fd_ringbuffer *ring,
+ const struct ir3_shader_variant *v, uint32_t dst_offset,
+ uint32_t offset, uint32_t size, const void *user_buffer,
+ struct pipe_resource *buffer)
+{
+ /* TODO inline this */
+ assert(dst_offset + size <= v->constlen * 4);
+ fd4_emit_const(ring, v->type, dst_offset,
+ offset, size, user_buffer, buffer);
+}
+
+static void
+emit_const_bo(struct fd_ringbuffer *ring,
+ const struct ir3_shader_variant *v, uint32_t dst_offset,
+ uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
+{
+ /* TODO inline this */
+ assert(dst_offset + num <= v->constlen * 4);
+ fd4_emit_const_bo(ring, v->type, dst_offset, num, prscs, offsets);
+}
+
static void
emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
/* note: PIPE_BUFFER disallowed for surfaces */
unsigned lvl = bufs[i]->u.tex.level;
- struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
+ struct fdl_slice *slice = fd_resource_slice(rsc, lvl);
unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
/* z32 restore is accomplished using depth write. If there is
PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
- OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
+ OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch) |
A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
OUT_RING(ring, 0x00000000);
OUT_RELOC(ring, rsc->bo, offset, 0, 0);
continue;
if (vp->inputs[i].sysval) {
switch(vp->inputs[i].slot) {
- case SYSTEM_VALUE_BASE_VERTEX:
- /* handled elsewhere */
- break;
case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
vertex_regid = vp->inputs[i].regid;
break;
uint32_t size = fd_bo_size(rsc->bo) - off;
debug_assert(fmt != ~0);
+#ifdef DEBUG
+ /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
+ */
+ if (off > fd_bo_size(rsc->bo))
+ continue;
+#endif
+
OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
- total_in += vp->inputs[i].ncomp;
+ total_in += util_bitcount(vp->inputs[i].compmask);
j++;
}
}
emit_marker(ring, 5);
- if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
+ if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
- bool fragz = fp->has_kill | fp->writes_pos;
- bool clamp = !ctx->rasterizer->depth_clip;
+ bool fragz = fp->no_earlyz | fp->writes_pos;
+ bool clamp = !ctx->rasterizer->depth_clip_near;
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, zsa->rb_depth_control |
COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
- COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
+ COND(fragz && fp->fragcoord_compmask != 0,
+ A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
/* maybe this register/bitfield needs a better name.. this
* appears to be just disabling early-z
OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
OUT_RING(ring, zsa->gras_alpha_control |
COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
- COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
+ COND(fragz && fp->fragcoord_compmask != 0,
+ A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
}
if (dirty & FD_DIRTY_RASTERIZER) {
OUT_RING(ring, rast->pc_prim_vtx_cntl2);
}
- if (dirty & FD_DIRTY_SCISSOR) {
+ /* NOTE: scissor enabled bit is part of rasterizer state: */
+ if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
ir3_emit_vs_consts(vp, ring, ctx, emit->info);
- if (!emit->key.binning_pass)
+ if (!emit->binning_pass)
ir3_emit_fs_consts(fp, ring, ctx);
}
bool is_int = util_format_is_pure_integer(format);
bool has_alpha = util_format_has_alpha(format);
uint32_t control = blend->rb_mrt[i].control;
- uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
if (is_int) {
control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
}
- if (has_alpha) {
- blend_control |= blend->rb_mrt[i].blend_control_rgb;
- } else {
- blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
+ if (!has_alpha) {
control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
}
OUT_RING(ring, control);
OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
- OUT_RING(ring, blend_control);
+ OUT_RING(ring, blend->rb_mrt[i].blend_control);
}
OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
fd_hw_query_enable(batch, ring);
}
-static void
-fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
-{
- __OUT_IB(ring, true, target);
-}
-
static void
fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
unsigned dst_off, struct pipe_resource *src, unsigned src_off,
for (i = 0; i < sizedwords; i++) {
OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
OUT_RING(ring, 0x00000000);
- OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
- OUT_RELOC (ring, src_bo, src_off, 0, 0);
+ OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
+ OUT_RELOC(ring, src_bo, src_off, 0, 0);
dst_off += 4;
src_off += 4;
}
}
+void
+fd4_emit_init_screen(struct pipe_screen *pscreen)
+{
+ struct fd_screen *screen = fd_screen(pscreen);
+
+ screen->emit_ib = fd4_emit_ib;
+ screen->mem_to_mem = fd4_mem_to_mem;
+}
+
void
fd4_emit_init(struct pipe_context *pctx)
{
- struct fd_context *ctx = fd_context(pctx);
- ctx->emit_const = fd4_emit_const;
- ctx->emit_const_bo = fd4_emit_const_bo;
- ctx->emit_ib = fd4_emit_ib;
- ctx->mem_to_mem = fd4_mem_to_mem;
}
projects / mesa.git / blobdiff