freedreno: fix off-by-one in assertions checking for const sizes

[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 8d07ceff9bbdec1ddbf783be10ef5b48cf636b93..0aff8fe3e2f19f48507467b99042dbbc886f972e 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -43,6 +43,8 @@
 #include "fd4_format.h"
 #include "fd4_zsa.h"
 
+#include "ir3_const.h"
+
 /* regid:          base const register
  * prsc or dwords: buffer containing constant values
  * sizedwords:     size of const value buffer
@@ -86,7 +88,7 @@ fd4_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
 }
 
 static void
-fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
+fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type,
                uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
 {
        uint32_t anum = align(num, 4);
@@ -104,11 +106,7 @@ fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean writ
 
        for (i = 0; i < num; i++) {
                if (prscs[i]) {
-                       if (write) {
-                               OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
-                       } else {
-                               OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
-                       }
+                       OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
                } else {
                        OUT_RING(ring, 0xbad00000 | (i << 16));
                }
@@ -118,6 +116,34 @@ fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean writ
                OUT_RING(ring, 0xffffffff);
 }
 
+static bool
+is_stateobj(struct fd_ringbuffer *ring)
+{
+       return false;
+}
+
+void
+emit_const(struct fd_ringbuffer *ring,
+               const struct ir3_shader_variant *v, uint32_t dst_offset,
+               uint32_t offset, uint32_t size, const void *user_buffer,
+               struct pipe_resource *buffer)
+{
+       /* TODO inline this */
+       assert(dst_offset + size <= v->constlen * 4);
+       fd4_emit_const(ring, v->type, dst_offset,
+                       offset, size, user_buffer, buffer);
+}
+
+static void
+emit_const_bo(struct fd_ringbuffer *ring,
+               const struct ir3_shader_variant *v, uint32_t dst_offset,
+               uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
+{
+       /* TODO inline this */
+       assert(dst_offset + num <= v->constlen * 4);
+       fd4_emit_const_bo(ring, v->type, dst_offset, num, prscs, offsets);
+}
+
 static void
 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
                enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
@@ -323,7 +349,7 @@ fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
                                                        PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
                        OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
                                        A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
-                       OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->layout.cpp) |
+                       OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch) |
                                        A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
                        OUT_RING(ring, 0x00000000);
                        OUT_RELOC(ring, rsc->bo, offset, 0, 0);
@@ -562,7 +588,8 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                OUT_RING(ring, zsa->rb_depth_control |
                                COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
                                COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
-                               COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
+                               COND(fragz && fp->fragcoord_compmask != 0,
+                                               A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
 
                /* maybe this register/bitfield needs a better name.. this
                 * appears to be just disabling early-z
@@ -570,7 +597,8 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
                OUT_RING(ring, zsa->gras_alpha_control |
                                COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
-                               COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
+                               COND(fragz && fp->fragcoord_compmask != 0,
+                                               A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
        }
 
        if (dirty & FD_DIRTY_RASTERIZER) {
@@ -917,8 +945,8 @@ fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
        for (i = 0; i < sizedwords; i++) {
                OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
                OUT_RING(ring, 0x00000000);
-               OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
-               OUT_RELOC (ring, src_bo, src_off, 0, 0);
+               OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
+               OUT_RELOC(ring, src_bo, src_off, 0, 0);
 
                dst_off += 4;
                src_off += 4;
@@ -930,8 +958,6 @@ fd4_emit_init_screen(struct pipe_screen *pscreen)
 {
        struct fd_screen *screen = fd_screen(pscreen);
 
-       screen->emit_const = fd4_emit_const;
-       screen->emit_const_bo = fd4_emit_const_bo;
        screen->emit_ib = fd4_emit_ib;
        screen->mem_to_mem = fd4_mem_to_mem;
 }