freedreno: import libdrm_freedreno + redesign submit

[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 0f7c64703302c89c3854c8df7f09fde6739eb15e..49ce6353526b171256e54c0996fe94c7f83c16d4 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
 /*
  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
  *
@@ -190,6 +188,8 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
                        OUT_RING(ring, view->texconst3);
                        if (view->base.texture) {
                                struct fd_resource *rsc = fd_resource(view->base.texture);
+                               if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
+                                       rsc = rsc->stencil;
                                OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
                        } else {
                                OUT_RING(ring, 0x00000000);
@@ -296,7 +296,7 @@ fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
                         */
                        if (rsc->stencil && (i == 0)) {
                                rsc = rsc->stencil;
-                               format = fd_gmem_restore_format(rsc->base.b.format);
+                               format = fd_gmem_restore_format(rsc->base.format);
                        }
 
                        /* note: PIPE_BUFFER disallowed for surfaces */
@@ -376,7 +376,7 @@ fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
                        continue;
                if (vp->inputs[i].sysval) {
                        switch(vp->inputs[i].slot) {
-                       case SYSTEM_VALUE_BASE_VERTEX:
+                       case SYSTEM_VALUE_FIRST_VERTEX:
                                /* handled elsewhere */
                                break;
                        case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
@@ -416,6 +416,13 @@ fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
                        uint32_t size = fd_bo_size(rsc->bo) - off;
                        debug_assert(fmt != ~0);
 
+#ifdef DEBUG
+                       /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
+                        */
+                       if (off > fd_bo_size(rsc->bo))
+                               continue;
+#endif
+
                        OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
                        OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
                                        A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
@@ -503,7 +510,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
        emit_marker(ring, 5);
 
-       if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
+       if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
                struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
                unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 
@@ -552,7 +559,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
        if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
                struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
                bool fragz = fp->has_kill | fp->writes_pos;
-               bool clamp = !ctx->rasterizer->depth_clip;
+               bool clamp = !ctx->rasterizer->depth_clip_near;
 
                OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
                OUT_RING(ring, zsa->rb_depth_control |
@@ -617,7 +624,8 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                OUT_RING(ring, rast->pc_prim_vtx_cntl2);
        }
 
-       if (dirty & FD_DIRTY_SCISSOR) {
+       /* NOTE: scissor enabled bit is part of rasterizer state: */
+       if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
                struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 
                OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
@@ -678,7 +686,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
        if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
                ir3_emit_vs_consts(vp, ring, ctx, emit->info);
-               if (!emit->key.binning_pass)
+               if (!emit->binning_pass)
                        ir3_emit_fs_consts(fp, ring, ctx);
        }
 
@@ -910,6 +918,26 @@ fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
        __OUT_IB(ring, true, target);
 }
 
+static void
+fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
+               unsigned dst_off, struct pipe_resource *src, unsigned src_off,
+               unsigned sizedwords)
+{
+       struct fd_bo *src_bo = fd_resource(src)->bo;
+       struct fd_bo *dst_bo = fd_resource(dst)->bo;
+       unsigned i;
+
+       for (i = 0; i < sizedwords; i++) {
+               OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
+               OUT_RING(ring, 0x00000000);
+               OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
+               OUT_RELOC (ring, src_bo, src_off, 0, 0);
+
+               dst_off += 4;
+               src_off += 4;
+       }
+}
+
 void
 fd4_emit_init(struct pipe_context *pctx)
 {
@@ -917,4 +945,5 @@ fd4_emit_init(struct pipe_context *pctx)
        ctx->emit_const = fd4_emit_const;
        ctx->emit_const_bo = fd4_emit_const_bo;
        ctx->emit_ib = fd4_emit_ib;
+       ctx->mem_to_mem = fd4_mem_to_mem;
 }