if (rsc->stencil) {
rsc = rsc->stencil;
pformat = rsc->base.b.format;
- bases++;
+ if (bases)
+ bases++;
}
slice = fd_resource_slice(rsc, psurf->u.tex.level);
}
}
+static bool
+use_hw_binning(struct fd_batch *batch)
+{
+ struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+
+ /* this seems to be a hw bug.. but this hack fixes piglit fbo-maxsize: */
+ if ((pfb->width > 4096) && (pfb->height > 4096))
+ return false;
+
+ return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
+}
+
/* transfer from gmem to system memory (ie. normal RAM) */
static void
-emit_gmem2mem_surf(struct fd_context *ctx, bool stencil,
+emit_gmem2mem_surf(struct fd_batch *batch, bool stencil,
uint32_t base, struct pipe_surface *psurf)
{
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
struct fd_resource *rsc = fd_resource(psurf->texture);
enum pipe_format pformat = psurf->format;
struct fd_resource_slice *slice;
A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
- fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+ fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
-fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
{
+ struct fd_context *ctx = batch->ctx;
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct fd_ringbuffer *ring = ctx->ring;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd4_emit emit = {
+ .debug = &ctx->debug,
.vtx = &fd4_ctx->solid_vbuf_state,
.prog = &ctx->solid_prog,
.key = {
OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
- fd_wfi(ctx, ring);
+ fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
fd4_program_emit(ring, &emit, 0, NULL);
fd4_emit_vertex_bufs(ring, &emit);
- if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+ if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
- if (!rsc->stencil || (ctx->resolve & FD_BUFFER_DEPTH))
- emit_gmem2mem_surf(ctx, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
- if (rsc->stencil && (ctx->resolve & FD_BUFFER_STENCIL))
- emit_gmem2mem_surf(ctx, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
+ if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
+ emit_gmem2mem_surf(batch, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
+ if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
+ emit_gmem2mem_surf(batch, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
}
- if (ctx->resolve & FD_BUFFER_COLOR) {
+ if (batch->resolve & FD_BUFFER_COLOR) {
unsigned i;
for (i = 0; i < pfb->nr_cbufs; i++) {
if (!pfb->cbufs[i])
continue;
- if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
+ if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
continue;
- emit_gmem2mem_surf(ctx, false, gmem->cbuf_base[i], pfb->cbufs[i]);
+ emit_gmem2mem_surf(batch, false, gmem->cbuf_base[i], pfb->cbufs[i]);
}
}
/* transfer from system memory to gmem */
static void
-emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
+emit_mem2gmem_surf(struct fd_batch *batch, uint32_t *bases,
struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
{
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
struct pipe_surface *zsbufs[2];
emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
- fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+ fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
}
static void
-fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
{
+ struct fd_context *ctx = batch->ctx;
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct fd_ringbuffer *ring = ctx->ring;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd4_emit emit = {
+ .debug = &ctx->debug,
.vtx = &fd4_ctx->blit_vbuf_state,
.sprite_coord_enable = 1,
/* NOTE: They all use the same VP, this is for vtx bufs. */
mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
- OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
- A4XX_RB_MRT_CONTROL_B11 |
+ OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
bin_w = gmem->bin_w;
bin_h = gmem->bin_h;
- if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
+ if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
emit.fp = NULL; /* frag shader changed so clear cache */
fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
- emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
+ emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
}
- if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+ if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
switch (pfb->zsbuf->format) {
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
case PIPE_FORMAT_Z32_FLOAT:
}
emit.fp = NULL; /* frag shader changed so clear cache */
fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
- emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
+ emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
}
OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
}
static void
-patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
+patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
- for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
- struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
+ for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
+ struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
}
- util_dynarray_resize(&ctx->draw_patches, 0);
-}
-
-static void
-patch_rbrc(struct fd_context *ctx, uint32_t val)
-{
- struct fd4_context *fd4_ctx = fd4_context(ctx);
- unsigned i;
- for (i = 0; i < fd_patch_num_elements(&fd4_ctx->rbrc_patches); i++) {
- struct fd_cs_patch *patch = fd_patch_element(&fd4_ctx->rbrc_patches, i);
- *patch->cs = patch->val | val;
- }
- util_dynarray_resize(&fd4_ctx->rbrc_patches, 0);
+ util_dynarray_resize(&batch->draw_patches, 0);
}
/* for rendering directly to system memory: */
static void
-fd4_emit_sysmem_prep(struct fd_context *ctx)
+fd4_emit_sysmem_prep(struct fd_batch *batch)
{
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
- struct fd_ringbuffer *ring = ctx->ring;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
- fd4_emit_restore(ctx);
+ fd4_emit_restore(batch, ring);
OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
A4XX_RB_MODE_CONTROL_HEIGHT(0) |
0x00c00000); /* XXX */
- patch_draws(ctx, IGNORE_VISIBILITY);
- patch_rbrc(ctx, 0); // XXX
+ OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
+ OUT_RING(ring, 0x8);
+
+ patch_draws(batch, IGNORE_VISIBILITY);
}
static void
-update_vsc_pipe(struct fd_context *ctx)
+update_vsc_pipe(struct fd_batch *batch)
{
+ struct fd_context *ctx = batch->ctx;
struct fd4_context *fd4_ctx = fd4_context(ctx);
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_ringbuffer *ring = batch->gmem;
int i;
OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
}
}
-/* before first tile */
static void
-fd4_emit_tile_init(struct fd_context *ctx)
+emit_binning_pass(struct fd_batch *batch)
{
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_context *ctx = batch->ctx;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- uint32_t rb_render_control;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
+ int i;
+
+ uint32_t x1 = gmem->minx;
+ uint32_t y1 = gmem->miny;
+ uint32_t x2 = gmem->minx + gmem->width - 1;
+ uint32_t y2 = gmem->miny + gmem->height - 1;
+
+ OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
+ OUT_RING(ring, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE);
+
+ OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
+ OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
+ A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
+ A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+ A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+
+ OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
+ OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
+ A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
+
+ /* setup scissor/offset for whole screen: */
+ OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
+ OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(x1) |
+ A4XX_RB_BIN_OFFSET_Y(y1));
+
+ OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
+ OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
+ A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
+ OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
+ A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
+
+ for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
+ OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
+ OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
+ A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
+ }
+
+ /* emit IB to binning drawcmds: */
+ ctx->emit_ib(ring, batch->binning);
+
+ fd_reset_wfi(batch);
+ fd_wfi(batch, ring);
- fd4_emit_restore(ctx);
+ /* and then put stuff back the way it was: */
+
+ OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
+ OUT_RING(ring, 0x00000000);
+
+ OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
+ OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
+ A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
+ A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
+ A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+
+ fd_event_write(batch, ring, CACHE_FLUSH);
+ fd_wfi(batch, ring);
+}
+
+/* before first tile */
+static void
+fd4_emit_tile_init(struct fd_batch *batch)
+{
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+
+ fd4_emit_restore(batch, ring);
OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
+ update_vsc_pipe(batch);
+
+ fd_wfi(batch, ring);
+ OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
+ OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
+ A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
+
+ if (use_hw_binning(batch)) {
+ OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
+ OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
+ A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
+
+ OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
+ OUT_RING(ring, A4XX_RB_RENDER_CONTROL_BINNING_PASS |
+ A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
+ 0x8);
+
+ /* emit hw binning pass: */
+ emit_binning_pass(batch);
+
+ patch_draws(batch, USE_VISIBILITY);
+ } else {
+ patch_draws(batch, IGNORE_VISIBILITY);
+ }
+
OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
- 0x00010000); /* XXX */
-
- update_vsc_pipe(ctx);
- patch_draws(ctx, IGNORE_VISIBILITY);
-
- rb_render_control = 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
- patch_rbrc(ctx, rb_render_control);
+ A4XX_RB_MODE_CONTROL_ENABLE_GMEM);
}
/* before mem2gmem */
static void
-fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
{
- struct fd_ringbuffer *ring = ctx->ring;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct fd_context *ctx = batch->ctx;
+ struct fd_ringbuffer *ring = batch->gmem;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
if (pfb->zsbuf) {
} else {
OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
}
-
- if (ctx->needs_rb_fbd) {
- fd_wfi(ctx, ring);
- OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
- OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
- A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
- ctx->needs_rb_fbd = false;
- }
}
/* before IB to rendering cmds: */
static void
-fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
{
- struct fd_ringbuffer *ring = ctx->ring;
+ struct fd_context *ctx = batch->ctx;
+ struct fd4_context *fd4_ctx = fd4_context(ctx);
+ struct fd_ringbuffer *ring = batch->gmem;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
uint32_t x1 = tile->xoff;
uint32_t y1 = tile->yoff;
uint32_t x2 = tile->xoff + tile->bin_w - 1;
uint32_t y2 = tile->yoff + tile->bin_h - 1;
+ if (use_hw_binning(batch)) {
+ struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
+
+ assert(pipe->w * pipe->h);
+
+ fd_event_write(batch, ring, HLSQ_FLUSH);
+ fd_wfi(batch, ring);
+
+ OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
+ OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
+ A4XX_PC_VSTREAM_CONTROL_N(tile->n));
+
+ OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
+ OUT_RELOCW(ring, pipe->bo, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
+ OUT_RELOCW(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
+ (tile->p * 4), 0, 0);
+ } else {
+ OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
+ OUT_RING(ring, 0x00000000);
+ }
+
OUT_PKT3(ring, CP_SET_BIN, 3);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
+
+ OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
+ OUT_RING(ring, 0x8);
}
void
projects / mesa.git / blobdiff