freedreno: drop needs_rb_fbd

[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_gmem.c

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index afd37a88f43fc3bfad68834c8b1217b5b3881032..32541fe06f02f8fe7b584e6d5e12f2bdd5856d28 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -228,7 +228,7 @@ fd4_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
        OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
        OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 
-       fd_wfi(ctx, ring);
+       fd_wfi(batch, ring);
 
        OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
        OUT_RING(ring, 0x80000);      /* GRAS_CL_CLIP_CNTL */
@@ -527,7 +527,7 @@ fd4_emit_sysmem_prep(struct fd_batch *batch)
        struct pipe_framebuffer_state *pfb = &batch->framebuffer;
        struct fd_ringbuffer *ring = batch->gmem;
 
-       fd4_emit_restore(batch->ctx, ring);
+       fd4_emit_restore(batch, ring);
 
        OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
        OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
@@ -641,8 +641,8 @@ emit_binning_pass(struct fd_batch *batch)
        /* emit IB to binning drawcmds: */
        ctx->emit_ib(ring, batch->binning);
 
-       fd_reset_wfi(ctx);
-       fd_wfi(ctx, ring);
+       fd_reset_wfi(batch);
+       fd_wfi(batch, ring);
 
        /* and then put stuff back the way it was: */
 
@@ -655,8 +655,8 @@ emit_binning_pass(struct fd_batch *batch)
                        A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
                        A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 
-       fd_event_write(ctx, ring, CACHE_FLUSH);
-       fd_wfi(ctx, ring);
+       fd_event_write(batch, ring, CACHE_FLUSH);
+       fd_wfi(batch, ring);
 }
 
 /* before first tile */
@@ -664,9 +664,10 @@ static void
 fd4_emit_tile_init(struct fd_batch *batch)
 {
        struct fd_ringbuffer *ring = batch->gmem;
+       struct pipe_framebuffer_state *pfb = &batch->framebuffer;
        struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
 
-       fd4_emit_restore(batch->ctx, ring);
+       fd4_emit_restore(batch, ring);
 
        OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
        OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
@@ -674,6 +675,11 @@ fd4_emit_tile_init(struct fd_batch *batch)
 
        update_vsc_pipe(batch);
 
+       fd_wfi(batch, ring);
+       OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
+       OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
+                       A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
+
        if (use_hw_binning(batch)) {
                OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
                OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
@@ -744,14 +750,6 @@ fd4_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
        } else {
                OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
        }
-
-       if (ctx->needs_rb_fbd) {
-               fd_wfi(ctx, ring);
-               OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
-               OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
-                               A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
-               ctx->needs_rb_fbd = false;
-       }
 }
 
 /* before IB to rendering cmds: */
@@ -774,8 +772,8 @@ fd4_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 
                assert(pipe->w * pipe->h);
 
-               fd_event_write(ctx, ring, HLSQ_FLUSH);
-               fd_wfi(ctx, ring);
+               fd_event_write(batch, ring, HLSQ_FLUSH);
+               fd_wfi(batch, ring);
 
                OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
                OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |