radeonsi: extract TGSI memory/texture opcode handling into its own file

[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_rasterizer.c

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c b/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c
index d894b6b9e096fd51af1461e9688457b8deac8952..b3a42929c50cdafbae177baedb046a9bbd49727a 100644 (file)
--- a/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c
@@ -77,6 +77,13 @@ fd4_rasterizer_state_create(struct pipe_context *pctx,
 
        so->gras_su_mode_control =
                        A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(cso->line_width/2.0);
+       so->pc_prim_vtx_cntl2 =
+               A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(fd_polygon_mode(cso->fill_front)) |
+               A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(fd_polygon_mode(cso->fill_back));
+
+       if (cso->fill_front != PIPE_POLYGON_MODE_FILL ||
+               cso->fill_back != PIPE_POLYGON_MODE_FILL)
+               so->pc_prim_vtx_cntl2 |= A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE;
 
        if (cso->cull_face & PIPE_FACE_FRONT)
                so->gras_su_mode_control |= A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT;
@@ -91,7 +98,8 @@ fd4_rasterizer_state_create(struct pipe_context *pctx,
                so->gras_su_mode_control |= A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET;
 
        if (!cso->depth_clip)
-               so->gras_cl_clip_cntl |= A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE;
+               so->gras_cl_clip_cntl |= A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE |
+                       A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE;
        if (cso->clip_halfz)
                so->gras_cl_clip_cntl |= A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z;