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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a5xx / a5xx.xml.h
diff --git a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
index c50dfb2d19b566be5a0362fcb9d4278ca2101694..76098b2824c69e717a6d489abce5c8aff27237f2 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
+++ b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
@@ -8,15 +8,15 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  27744 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-04-14 19:13:31)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 102364 bytes, from 2017-04-14 19:14:25)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-04-14 19:13:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-17 13:21:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31541 bytes, from 2017-05-17 13:21:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110757 bytes, from 2017-05-17 13:21:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 105446 bytes, from 2017-05-17 20:33:08)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)
 
 Copyright (C) 2013-2017 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -45,7 +45,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 enum a5xx_color_fmt {
+       RB5_A8_UNORM = 2,
        RB5_R8_UNORM = 3,
+       RB5_R8_SNORM = 4,
        RB5_R8_UINT = 5,
        RB5_R8_SINT = 6,
        RB5_R4G4B4A4_UNORM = 8,
@@ -62,6 +64,7 @@ enum a5xx_color_fmt {
        RB5_R16_SINT = 25,
        RB5_R8G8B8A8_UNORM = 48,
        RB5_R8G8B8_UNORM = 49,
+       RB5_R8G8B8A8_SNORM = 50,
        RB5_R8G8B8A8_UINT = 51,
        RB5_R8G8B8A8_SINT = 52,
        RB5_R10G10B10A2_UNORM = 55,
@@ -75,6 +78,8 @@ enum a5xx_color_fmt {
        RB5_R32_FLOAT = 74,
        RB5_R32_UINT = 75,
        RB5_R32_SINT = 76,
+       RB5_R16G16B16A16_UNORM = 96,
+       RB5_R16G16B16A16_SNORM = 97,
        RB5_R16G16B16A16_FLOAT = 98,
        RB5_R16G16B16A16_UINT = 99,
        RB5_R16G16B16A16_SINT = 100,
@@ -158,6 +163,7 @@ enum a5xx_vtx_fmt {
 enum a5xx_tex_fmt {
        TFMT5_A8_UNORM = 2,
        TFMT5_8_UNORM = 3,
+       TFMT5_8_SNORM = 4,
        TFMT5_8_UINT = 5,
        TFMT5_8_SINT = 6,
        TFMT5_4_4_4_4_UNORM = 8,
@@ -175,7 +181,7 @@ enum a5xx_tex_fmt {
        TFMT5_16_SINT = 25,
        TFMT5_8_8_8_8_UNORM = 48,
        TFMT5_8_8_8_UNORM = 49,
-       TFMT5_8_8_8_SNORM = 50,
+       TFMT5_8_8_8_8_SNORM = 50,
        TFMT5_8_8_8_8_UINT = 51,
        TFMT5_8_8_8_8_SINT = 52,
        TFMT5_9_9_9_E5_FLOAT = 53,
@@ -190,6 +196,8 @@ enum a5xx_tex_fmt {
        TFMT5_32_FLOAT = 74,
        TFMT5_32_UINT = 75,
        TFMT5_32_SINT = 76,
+       TFMT5_16_16_16_16_UNORM = 96,
+       TFMT5_16_16_16_16_SNORM = 97,
        TFMT5_16_16_16_16_FLOAT = 98,
        TFMT5_16_16_16_16_UINT = 99,
        TFMT5_16_16_16_16_SINT = 100,
@@ -200,6 +208,10 @@ enum a5xx_tex_fmt {
        TFMT5_32_32_32_32_UINT = 131,
        TFMT5_32_32_32_32_SINT = 132,
        TFMT5_X8Z24_UNORM = 160,
+       TFMT5_RGTC1_UNORM = 183,
+       TFMT5_RGTC1_SNORM = 184,
+       TFMT5_RGTC2_UNORM = 187,
+       TFMT5_RGTC2_SNORM = 188,
 };
 
 enum a5xx_tex_fetchsize {
@@ -1337,25 +1349,85 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
 
 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL                        0x0000f810
 
-#define REG_A5XX_VSC_PIPE_DATA_LENGTH_0                                0x00000c00
+#define REG_A5XX_VSC_BIN_SIZE                                  0x00000bc2
+#define A5XX_VSC_BIN_SIZE_WIDTH__MASK                          0x000000ff
+#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT                         0
+static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
+{
+       assert(!(val & 0x1f));
+       return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
+}
+#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK                         0x0001fe00
+#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT                                9
+static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
+{
+       assert(!(val & 0x1f));
+       return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
+}
+
+#define REG_A5XX_VSC_SIZE_ADDRESS_LO                           0x00000bc3
+
+#define REG_A5XX_VSC_SIZE_ADDRESS_HI                           0x00000bc4
+
+#define REG_A5XX_UNKNOWN_0BC5                                  0x00000bc5
+
+#define REG_A5XX_UNKNOWN_0BC6                                  0x00000bc6
+
+static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
+#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK                       0x000003ff
+#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT                      0
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
+}
+#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK                       0x000ffc00
+#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT                      10
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
+}
+#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK                       0x00f00000
+#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT                      20
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
+}
+#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK                       0x0f000000
+#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT                      24
+static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
+{
+       return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
+}
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
+
+static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
 
 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0                         0x00000c60
 
 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1                         0x00000c61
 
-#define REG_A5XX_VSC_BIN_SIZE                                  0x00000cdd
-#define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE                        0x80000000
-#define A5XX_VSC_BIN_SIZE_X__MASK                              0x00007fff
-#define A5XX_VSC_BIN_SIZE_X__SHIFT                             0
-static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val)
+#define REG_A5XX_VSC_RESOLVE_CNTL                              0x00000cdd
+#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE            0x80000000
+#define A5XX_VSC_RESOLVE_CNTL_X__MASK                          0x00007fff
+#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT                         0
+static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
 {
-       return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK;
+       return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
 }
-#define A5XX_VSC_BIN_SIZE_Y__MASK                              0x7fff0000
-#define A5XX_VSC_BIN_SIZE_Y__SHIFT                             16
-static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
+#define A5XX_VSC_RESOLVE_CNTL_Y__MASK                          0x7fff0000
+#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT                         16
+static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
 {
-       return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK;
+       return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
 }
 
 #define REG_A5XX_GRAS_ADDR_MODE_CNTL                           0x00000c81
@@ -1518,6 +1590,7 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
 #define REG_A5XX_VPC_ADDR_MODE_CNTL                            0x00000e61
 
 #define REG_A5XX_VPC_MODE_CNTL                                 0x00000e62
+#define A5XX_VPC_MODE_CNTL_BINNING_PASS                                0x00000001
 
 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0                         0x00000e64
 
@@ -2103,6 +2176,7 @@ static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_dep
 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL                 0x0000e099
 
 #define REG_A5XX_GRAS_SC_CNTL                                  0x0000e0a0
+#define A5XX_GRAS_SC_CNTL_BINNING_PASS                         0x00000001
 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED                       0x00008000
 
 #define REG_A5XX_GRAS_SC_BIN_CNTL                              0x0000e0a1
@@ -2246,7 +2320,9 @@ static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
 #define A5XX_RB_CNTL_BYPASS                                    0x00020000
 
 #define REG_A5XX_RB_RENDER_CNTL                                        0x0000e141
+#define A5XX_RB_RENDER_CNTL_BINNING_PASS                       0x00000001
 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED                     0x00000040
+#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE                 0x00000080
 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH                         0x00004000
 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2                                0x00008000
 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK                    0x00ff0000
@@ -2744,6 +2820,9 @@ static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
        return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
 }
 
+#define REG_A5XX_RB_SAMPLE_COUNT_CONTROL                       0x0000e1d1
+#define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY                      0x00000002
+
 #define REG_A5XX_RB_BLIT_CNTL                                  0x0000e210
 #define A5XX_RB_BLIT_CNTL_BUF__MASK                            0x0000000f
 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT                           0
@@ -2875,6 +2954,10 @@ static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
        return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
 }
 
+#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO                       0x0000e267
+
+#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI                       0x0000e268
+
 #define REG_A5XX_VPC_CNTL_0                                    0x0000e280
 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK                    0x0000007f
 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT                   0
@@ -2986,6 +3069,7 @@ static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
 {
        return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
 }
+#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST              0x00000400
 
 #define REG_A5XX_PC_PRIM_VTX_CNTL                              0x0000e385
 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE                            0x00000800